Capacitive Galvanic Isolator Using Staggered Pulse Arrays
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Solution Overview
Problem
Electronic isolation systems face challenges in communicating between devices operating in different power domains without direct electrical connections, as existing galvanic isolators can be prone to common mode noise and signal distortion due to the limitations of capacitive and optocouplers in transmitting fully differential signals across galvanic isolation barriers.
Innovation Solution
A capacitive isolator design using an array of input capacitors, where each capacitor receives input pulses offset from others, extending the pulse duration, and a galvanic isolation capacitor connected at a floating node, allowing for efficient transmission of electrical signals across a galvanic isolation barrier by matching the delay to the rise time of the pulse, thereby reducing common mode noise and enhancing signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If a single capacitor is used for galvanic isolation, then the device structure is simple, but the pulse duration is insufficient and signal integrity is poor
Solution Approach 1:
The patent divides a single capacitor into multiple segmented capacitors (first capacitor, second capacitor, third capacitor) connected in parallel. Each capacitor receives a staggered input pulse, and their combined outputs create an extended pulse duration at the receiver side, resolving the contradiction between simple structure and sufficient pulse duration.
Solution Approach 2:
The patent employs periodic action by applying staggered input pulses to multiple capacitors at different time intervals. The first capacitor receives a pulse at time t1, the second at t2, and the third at t3, creating overlapping output pulses that extend the overall pulse duration and improve signal integrity across the galvanic isolation barrier.
2Reliability
If capacitive isolators are used to transmit signals across galvanic isolation barriers, then electrical isolation is achieved, but common mode noise and signal distortion occur
Solution Approach 1:
The patent connects the capacitors in parallel configuration with their outputs tied together at the receiver side, creating an equipotential node that sums the individual capacitor outputs. This equipotential connection ensures that common mode noise affecting individual capacitors is rejected, while differential signals are properly transmitted, improving signal integrity across the galvanic isolation barrier.
3Duration of action of moving object
If input pulses are applied simultaneously to all capacitors, then the circuit operation is simple, but the pulse duration extension effect is not achieved
Solution Approach 1:
The patent implements preliminary action by pre-calculating and pre-setting the staggered timing intervals for input pulses applied to each capacitor. The delay between pulses to different capacitors is designed in advance to match the capacitor charging/discharging characteristics, ensuring that output pulses from each capacitor overlap constructively to extend the overall pulse duration without requiring complex real-time control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively transmits signals across galvanic isolation barriers with improved noise rejection and signal integrity, allowing for robust communication between isolated devices by extending pulse duration and aligning delays with the rise time of the pulse, thus simplifying receiver architecture and reducing power dissipation.
Implementation Method 1
capacitive couplers transmit electrical signals from a first circuit to a second circuit that is electrically isolated through electric fields
Implementation Method 2
an isolation barrier that electrically isolates the input side from the output side
Data Source
AI summary
An isolator, circuit, and isolation method are disclosed. An illustrative capacitive isolator is disclosed to include an input side that receives an electrical input signal, an output side that outputs an electrical output signal, and an isolation barrier that electrically isolates the input side from the output side. The input side is further disclosed to include an array of input capacitors, where each capacitor in the array of input capacitors receives an input pulse based on the electrical input signal, where each capacitor in the array of input capacitors receives the input pulse offset from input pulses received at others of the capacitors in the array of input capacitors thereby extending a pulse duration of the electrical input signal.


