Capacitive Level Converter for High-Voltage CMOS Signal Shifting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional level converters in CMOS circuit technology face limitations in converting logic signal levels between different supply voltages, particularly when transistors can only endure less than 3V, making it challenging to convert signal levels beyond their electrical strength, such as from 0V to -3V using only MOS transistors.
Innovation Solution
The level converter employs a latch and inverter circuit with p-channel and n-channel transistors connected in series, utilizing a capacitor for feedback and voltage dividers to switch between signal levels, ensuring that at least one transistor is turned off at any time to prevent direct conductive paths and manage excess voltages, allowing conversion of signal levels up to ±5V or ±3V.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional CMOS level converters with two cross-coupled current paths are used, then signal level conversion between supply voltages is achieved, but the transistors can only endure less than 3V, limiting conversion capability to signal levels within their electrical strength
Solution Approach 1:
The level converter is divided into multiple functional blocks: a first converter stage with transistors for initial level conversion, a second converter stage with additional transistors for further conversion, and intermediate circuitry. This segmentation allows each transistor to operate within its 3V endurance while achieving overall conversion from 0V to -3V or beyond through staged conversion processes.
Solution Approach 2:
Intermediate circuit stages and components act as mediators between the input signal at one voltage level and the output signal at another voltage level. The first converter stage converts the input signal to an intermediate level that the second stage can then convert to the final output level, allowing transistors to handle only the voltage differences they can endure.
2Adaptability or versatility
If transistors are used to convert signal levels beyond their electrical strength (e.g., 0V to -3V), then higher voltage level conversion is achieved, but the transistors may be damaged by excess voltage
Solution Approach 1:
The circuit design incorporates protective mechanisms that cushion transistors from excess voltage before damage can occur. Voltage dividers and series-connected transistors are configured to limit the voltage across any single transistor to within its endurance rating, preventing damage before it happens.
Solution Approach 2:
The circuit dynamically adjusts operating parameters such as voltage distribution across transistors, current paths, and conduction states based on the input signal level. This allows the system to handle high voltage level conversions while keeping individual transistor stress within safe limits through real-time parameter modulation.
3Reliability
If voltage dividers and feedback capacitors are added to manage voltage levels, then transistor protection is improved, but circuit complexity increases
Solution Approach 1:
Circuit components are designed to perform multiple functions simultaneously. For example, series-connected transistors serve both as signal conduction paths and as voltage distribution elements that protect individual devices. Feedback capacitors not only provide stability but also participate in the level conversion process. This multi-functionality reduces the need for separate protective components.
Solution Approach 2:
Protective functions are merged into the signal conversion path itself rather than being added as separate parallel circuits. The voltage dividers and feedback mechanisms are integrated into the core conversion architecture, allowing protection and conversion to occur through the same components performing their primary conversion function.
Data Source
AI summary
A level converter for providing an output signal at a circuit output based on an input signal includes an output coupling circuit formed to provide an output signal based on a first partial output signal and a second partial output signal, a driver circuit formed to provide the second partial output signal such that the second partial output signal is switchable between two different signal levels depending on the state of the input signal, wherein an input of the driver circuit is capacitively coupled to the input of the level converter in order to allow for switching between the signal levels of the second partial output signal by the capacitive coupling in response to a change in the state of the input signal, and a holding circuit formed to keep the state of the second partial output signal constant in case of a constant state of the input signal.