Capacitive Level-Shift Circuit for Low-Power Data-Dependent Signals
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Solution Overview
Problem
Existing level-shift circuits for broadband communications are power hungry, consume large chip area, and fail to properly shift the '0' level of signals, especially when used with data-dependent digital signals and thin-oxide PMOS switches, leading to inefficiencies in high-resolution DAC circuits.
Innovation Solution
A low-power level-shift circuit using a PMOS switch biased with a high-voltage domain supply, coupled with a buffer circuit and a biasing circuit controlled by a synchronized clock signal, which translates low-voltage domain data-dependent signals to a high-voltage domain suitable for DAC operation, utilizing a voltage divider and a fast thin-oxide PMOS transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If existing level-shift circuits are used to convert low-voltage domain signals to high-voltage domain for DAC operation, then voltage level conversion is achieved, but power consumption increases significantly
Solution Approach 1:
The patent changes the operating parameters of the level-shift circuit by using a PMOS switch biased with high-voltage domain supply voltage and a synchronized clock signal, transforming the circuit from a power-hungry design to a low-power design while maintaining reliable signal conversion. The buffer circuit is biased by low-voltage domain voltage supply, and the coupling capacitor translates the voltage level efficiently.
Solution Approach 2:
The patent replaces traditional power-hungry level-shift mechanisms with a more efficient electrical field-based approach using PMOS switches and capacitive coupling. This substitution eliminates the need for power-intensive conversion mechanisms while achieving the same voltage level translation function.
2Area of stationary object
If traditional level-shift circuits are used, then voltage conversion is achieved, but chip area consumption increases
Solution Approach 1:
The level-shift circuit is segmented into distinct functional blocks: a buffer circuit biased by low-voltage domain voltage supply, a coupling capacitor for voltage translation, and a biasing circuit with PMOS switch controlled by high-voltage domain supply. This segmentation allows each component to be optimized for minimal area while maintaining translation accuracy.
Solution Approach 2:
The patent uses a thin-oxide PMOS switch that occupies minimal chip area while providing effective voltage level conversion. The capacitive coupling approach uses a simple coupling capacitor instead of bulky traditional level-shift structures, reducing overall chip area consumption.
3Speed
If existing level-shift circuits operate with data-dependent signals, then signal conversion is attempted, but digital data edge rate degradation occurs
Solution Approach 1:
The biasing circuit is controlled by a synchronized clock signal that operates periodically in sync with the data-dependent signals. This periodic control ensures that the PMOS switch and coupling capacitor are activated at the appropriate times to maintain fast edge rates while achieving reliable voltage conversion for data-dependent signals.
Solution Approach 2:
The synchronized clock signal provides feedback control to the biasing circuit, ensuring that the level-shift operation is coordinated with the incoming data signals. This feedback mechanism prevents edge rate degradation by timing the voltage translation to occur during appropriate phases of the data signal cycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces power consumption by more than a factor of 3, minimizes chip area, and prevents digital data edge rate degradation, enabling efficient operation in high-speed applications like 10-Gigabit Ethernet and other communication devices.
Implementation Method 1
coupling capacitor Cc coupled, at a first node 112, to an output node of the buffer circuit 110
Data Source
Figure 1A~1B
Figure 2A
Figure 2B
AI summary
A low-power level-shift circuit for data-dependent signals includes a buffer circuit, a coupling capacitor, and a biasing circuit. The buffer circuit is biased by a low-voltage domain voltage supply and configured to receive a data-dependent signal. The coupling capacitor is coupled, at a first node, to an output node of the buffer circuit. The biasing circuit is coupled to a second node of the coupling capacitor and a switch. The level-shift circuit can translate a voltage level of the received data-dependent signal to a high-voltage domain that is suitable for proper operation of the switch.