Capacitive-Coupled Level Shifter for High Common-Mode Rejection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing level shifter designs face challenges in high-speed gate driver applications, particularly in full-bridge, half-bridge, and non-isolated buck topologies, where high common mode rejection is crucial to ensure reliable output signals, and they often require high current consumption and large layout areas due to the need for high-voltage components and accurate parasitic modeling.
Innovation Solution
A capacitive-coupled level shifter design that uses a capacitive divider circuit with multiple capacitors to couple the input to a comparator circuit, along with a resistor ladder for DC biasing and a speed booster circuit to enhance gain, allowing for dynamic operation and high common mode rejection without the need for high-voltage cascode devices, thereby reducing layout area and voltage stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If cascoding high voltage devices is used to extend voltage range, then the voltage capability is improved, but the speed performance degrades and layout area increases
Solution Approach 1:
The voltage range extension is achieved by segmenting the voltage handling into two parts: the capacitive coupling network handles the high voltage differential swings, while the comparator and subsequent stages operate at lower voltages. This segmentation allows each component to be optimized for its specific voltage range, maintaining high speed performance while achieving extended voltage capability.
Solution Approach 2:
The capacitive coupling network acts as an intermediary between the high voltage differential input and the lower voltage comparator circuit. The capacitors transfer the high voltage signal swings to the comparator inputs, enabling the comparator to sense high voltage differences without requiring high voltage transistors in the comparison stage itself.
2Strength
If high voltage components are used to withstand input voltage range, then the voltage robustness is improved, but the layout area increases
Solution Approach 1:
The circuit segments voltage handling responsibilities: capacitors handle high voltage storage and coupling, while transistors operate at lower voltages. This allows the use of smaller transistors with reduced layout area while maintaining voltage robustness through the capacitive coupling network.
Solution Approach 2:
The invention changes the operating parameters of the comparator stage to lower voltages while using capacitors to handle the high voltage differential input. This parameter separation allows the use of standard low-voltage transistors in the comparator, reducing layout area while maintaining high voltage robustness through the capacitive coupling network.
3Reliability
If dynamic pulsing is used to refresh gate driver stage, then the common mode rejection is improved, but the current consumption increases
Solution Approach 1:
The capacitive coupling network is pre-charged to the appropriate voltage levels during the charging phase, preparing the circuit for high-speed differential signaling. This preliminary action allows the subsequent differential transitions to occur rapidly with minimal additional current, reducing overall power consumption while maintaining high common mode rejection.
Solution Approach 2:
The circuit uses periodic charging and discharging of the capacitive coupling network to maintain signal integrity and common mode rejection. The periodic refresh of the capacitive stages ensures accurate differential signaling while allowing the use of lower current levels during the actual comparison and output phases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitive-coupled level shifter achieves higher speed performance with reduced dependency on temperature and process variations, lower current consumption, and smaller chip area, while maintaining reliable operation across high voltage domains, effectively addressing the limitations of existing solutions.
Implementation Method 1
capacitive divider circuit with multiple capacitors to couple the input to a comparator circuit
Implementation Method 2
Since inductors and capacitors block any DC component of the signal, the control signal is transformed into a sequence of pulses
Implementation Method 3
a resistor ladder configured to fix a DC biasing point of the positive and the negative inputs of the comparator circuit
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A capacitive-coupled level shifter (102) includes: an input (200) having a positive input terminal (INP) and a negative input terminal (INN), the input configured to receive a modulated signal in a first voltage domain; a comparator circuit (202) configured to shift the modulated signal to a second voltage domain higher than the first voltage domain; and a capacitive divider circuit (204) comprising a first capacitive divider branch coupling the positive input terminal of the input to a positive input terminal (A) of the comparator circuit and a second capacitive divider branch coupling the negative input terminal of the input to a negative input terminal (B) of the comparator circuit. The first capacitive divider branch and the second capacitive divider branch are symmetric so as to cancel out a common mode voltage of the modulated signal. A level shifter system which includes the capacitive-coupled level shifter is also described.