Capacitive Level Shifter Circuit for Wide-Range Voltage Conversion
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Solution Overview
Problem
Existing level shifter circuits are limited in flexibility regarding voltage ranges and area occupation, as they rely on high-voltage transistors for reliability but lack adequate protection and efficiency in shifting signals between low and high voltage levels, especially in non-volatile memory devices.
Innovation Solution
A level shifter circuit design incorporating a first inverter stage operating at low voltage, a latch stage operating at high voltage, and capacitive elements to ensure proper signal switching, with adjustable biasing voltages for the latch stage to accommodate varying high and low voltage values, enhancing flexibility and reducing area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage transistors are used in level shifter circuits, then reliability is improved, but area occupation increases
Solution Approach 1:
The patent applies local quality by using different transistor types in different circuit regions: LV transistors with thin gate oxide are used in the input stage where low voltage operates, while HV transistors with thick gate oxide are used in the output stage where high voltage operates. This localized approach ensures each transistor operates within its safe voltage range, improving reliability without requiring all transistors to be large HV devices.
Solution Approach 2:
The level shifter circuit is segmented into distinct functional stages: an input stage using LV transistors and an output stage using HV transistors. This segmentation allows each stage to be optimized for its specific voltage requirement, reducing the overall area compared to using HV transistors throughout the entire circuit.
2Strength
If high-voltage transistors are used in level shifter circuits, then high voltage withstand capability is improved, but device complexity increases
Solution Approach 1:
The circuit structure is tailored to local voltage requirements: the input stage is designed for low voltage operation with LV transistors, while the output stage is designed for high voltage operation with HV transistors. This localized design simplifies the overall circuit by avoiding the need for complex protection mechanisms that would be required if HV transistors were used throughout.
3Area of moving object
If mixed LV and HV transistor solutions are used, then area occupation is reduced, but protection against voltage failure is insufficient
Solution Approach 1:
The patent ensures each transistor is protected by using LV transistors only in the low-voltage input stage and HV transistors only in the high-voltage output stage. This localized matching of transistor voltage ratings to stage voltage levels provides inherent protection against voltage failure without requiring additional protection circuits.
Solution Approach 2:
The circuit uses intermediate voltage levels and staged conversion: the input stage processes low voltage signals, and the output stage generates high voltage signals. This intermediate staging acts as a mediator that prevents direct exposure of LV transistors to high voltage, providing protection without area penalty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a highly flexible level shifter circuit with improved reliability and reduced area occupation, capable of efficiently shifting signals across a wide voltage range, suitable for non-volatile memory devices and other applications requiring high operating flexibility and low circuit complexity.
Implementation Method 1
A first capacitive element is connected between the output of the first input inverter stage and a first holding node
Data Source
AI summary
A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.