Capacitive Level Translation Circuit for Compact High-Voltage Drive
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Solution Overview
Problem
Existing driver chips for imaging systems require large chip substrate areas due to high-voltage transistors in DC coupled configurations, leading to increased costs, and existing capacitively coupled isolation circuits are too complex and area-intensive to fit hundreds of copies on a single chip.
Innovation Solution
A capacitively coupled level translation circuit with cross-conduction prevention mechanisms, including power-on reset and pseudo-differential sensing, allows for efficient high-voltage output control using capacitively coupled inverters, reducing chip area and complexity while preventing damage from simultaneous enabling of high and low-side transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DC coupled high-voltage transistors are used for level translation, then reliable high-voltage control is achieved, but chip area increases significantly
Solution Approach 1:
The patent introduces capacitive coupling as an intermediary mechanism between low-voltage logic signals and high-voltage output transistors. The capacitor couples the voltage transition from the inverter output to the high-voltage transistor gate, enabling level translation without direct DC connection. This intermediary approach allows reliable high-voltage control while eliminating the need for large isolation areas around each transistor, thus resolving the contradiction between reliability and chip area.
2Area of stationary object
If capacitively coupled isolation circuits are used to reduce area, then chip area decreases, but circuit complexity increases
Solution Approach 1:
The patent merges the level translation function and the isolation function into a single capacitive coupling stage. The inverter output directly drives the capacitor, which in turn drives the high-voltage transistor gate. This unified approach eliminates the need for separate isolation circuits, reducing overall circuit complexity while maintaining area efficiency. The merging of functions resolves the contradiction between reduced area and circuit complexity.
3Area of stationary object
If capacitive coupling is used for level translation, then chip area is reduced, but cross-conduction risk increases
Solution Approach 1:
The patent applies preliminary anti-action by designing the capacitive coupling circuit to inherently prevent cross-conduction before it can occur. The capacitor couples only the voltage transition (dV/dt) from the inverter output, and the circuit is designed so that both high-side and low-side output transistors cannot be simultaneously enabled. This preliminary prevention mechanism addresses the cross-conduction risk while maintaining the area benefits of capacitive coupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables lower-cost, more compact driver chips with faster operation and protection against cross-conduction issues, effectively translating low-voltage signals to high-voltage outputs for imaging systems without the need for large isolation areas.
Implementation Method 1
capacitively coupled level translation that requires less area
Data Source
AI summary
A voltage level translator circuit has a digital logic circuit having a digital logic signal, at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal, and a cross-coupled inverter pair having, the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor. A high-voltage driving circuit has two low-voltage input signals, two high-voltage output signals, a first signal being a high-side drive signal and a second signal being a low-side drive signal, two level translators, a first level translator corresponding to the high-side drive signal, and a second level translator corresponding to the low-side drive signal, the level translators including a digital logic circuit having a digital logic signal, at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal, and a cross-coupled inverter pair having, the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor.