Capacitive Load Driver With Pre-Charged Switch Gates
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Solution Overview
Problem
Existing charge reuse drivers for capacitive loads, such as piezoelectric micro-mirrors, face challenges in reducing power dissipation and improving resonance frequency due to limitations in switch turn-on time and resistance, especially when handling high voltages and varying capacitances.
Innovation Solution
The implementation of a charge reuse driver with multiple sub-stages and high-voltage switches that utilize a sequence of rising and falling edges to efficiently transfer charge between a load capacitance and tank capacitances, reducing power dissipation by increasing the number of sub-steps and optimizing switch resistance and turn-on times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the number of sub-steps N is increased to reduce power dissipation, then power consumption decreases by a factor of (N-1), but the switching time and device complexity increase
Solution Approach 1:
The voltage transition is divided into N sub-steps, where each sub-step transfers a fraction of the total voltage change. This segmentation allows the load capacitor to be charged/discharged in incremental steps through sequential switching of tank capacitors, reducing the voltage difference across switches during transitions and thereby reducing power dissipation by a factor of (N-1) compared to direct charging/discharging.
2Use of energy by moving object
If the number of sub-steps N is increased to reduce power dissipation, then power consumption decreases by a factor of (N-1), but the switching time increases
Solution Approach 1:
The tank capacitors are pre-charged to specific voltage levels (fractions of VHV) before the switching sequence begins. This preliminary charging allows the sequential switching to proceed efficiently with minimal additional charging time at each step, as the voltage differences to be transferred are already prepared and matched to the load capacitor's current state.
3Productivity
If high voltage switches with low resistance and fast turn-on times are used, then charge transfer efficiency improves, but device complexity and cost increase
Solution Approach 1:
The invention changes the voltage parameters during the switching process by using multiple tank capacitors with different voltage levels (fractions of VHV). This parameter variation allows standard switches to operate at lower voltage differences during each sub-step, reducing the required switch resistance and turn-on time specifications while maintaining overall high charge transfer efficiency through the multi-step process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power consumption and increases resonance frequency by allowing for efficient charge redistribution between the load and tank capacitances, achieving a power reduction factor proportional to the number of sub-steps, while maintaining low switch resistance and fast turn-on times.
Implementation Method 1
a load capacitance CL to be driven by a periodic signal provided at its charge node
Implementation Method 2
the load capacitance itself may be charged or discharged (e.g., depending on whether it is performed during the rising or falling edge of the periodic signal, respectively) through the tank capacitors
Data Source
Figure 1
Figure 2a)~2c)
Figure 3~4
AI summary
A method, comprising: - providing a load capacitance (CL) having a charge node (104); - providing a set of energy storage capacitances (C1), having respective charge nodes (101); - providing electronic switch circuitry (20) configured to be made selectively conductive to couple the charge node (104) of the load capacitance (CL) to respective charge nodes (101) of energy storage capacitances (C1) in the set of energy storage capacitances (C1), wherein the electronic switch circuitry (20) comprise a switched current path (T, L) through a first transistor (TT1) and a second transistor (TT2) including junction diodes (BD1, BD2), wherein the first transistor (TT1) has a current path therethrough between a first common node (SS) and the respective charge node (101) of an energy storage capacitance (C1) in the set of energy storage capacitances (C1, C2) and the second transistor (TT2) has a current path therethrough between the first common node (SS) and the charge node (104) of the load capacitance (CL), the first transistor (TT1) and the second transistor (TT2) having control terminals mutually coupled at a second common node (GG), the control terminals having a parasitic capacitance (CP). The method comprises pre-charging the parasitic capacitance (CP) of the control terminals of the first transistor (TT1) and the second transistor (TT2) mutually coupled at the second common node (GG) prior to making conductive the switched current path (T, L) through the first transistor (TT1) and the second transistor (TT2).