Capacitive Measurement Circuit With Parasitic Charge Cancellation

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Solution Overview

Problem

Capacitance measurement applications are hindered by parasitic capacitances associated with sense plates, switches, connections, and wiring, leading to performance degradation, particularly in charge transfer methods used for proximity detection and other capacitance measurement techniques.

Innovation Solution

A method is introduced to compensate for parasitic capacitances by using a current mirror structure to mirror and remove the additional charge added by parasitic capacitances during each charge transfer cycle, allowing for the adjustment of capacitance measurement without physical changes to the sensor structure, and enabling the integration of capacitive elements into standard CMOS integrated circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If charge transfer method is used for capacitance measurement, then measurement capability is achieved, but parasitic capacitances degrade measurement precision

Engineering Contradiction:
Improvecapacitance measurement precisionVSAvoidparasitic capacitance effect
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and separates the parasitic capacitance effect from the total measured capacitance by performing measurements in two distinct phases: first with the switch open (capturing only parasitic capacitance), then with the switch closed (capturing total capacitance including parasitic). The parasitic component is then subtracted to isolate the true capacitance value, effectively removing the harmful parasitic effect from the measurement.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs a preliminary measurement of parasitic capacitance before the actual capacitance measurement by opening the switch during a first time period. This preliminary action captures the parasitic capacitance value which is then used to compensate for the measurement taken during the second time period when the switch is closed, ensuring accurate capacitance measurement despite the presence of parasitic effects.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If sensitivity is increased by reducing effective capacitance value, then measurement sensitivity improves, but circuit complexity increases

Engineering Contradiction:
Improvemeasurement sensitivityVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent employs periodic switching of the switch between open and closed states during different time periods. This periodic action allows the circuit to alternately measure parasitic capacitance and total capacitance, enabling sensitivity enhancement through time-multiplexed measurements without requiring complex additional circuitry. The periodic switching simplifies the approach compared to continuous measurement methods.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent introduces dynamic control of the switch state to enable the circuit to adapt between measuring parasitic capacitance and total capacitance. This dynamic switching allows the effective capacitance to be adjusted in time, enabling sensitivity optimization without permanent circuit modifications. The dynamic approach provides flexibility to balance sensitivity and complexity requirements.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances sensitivity by removing unwanted capacitance, allows for practical implementation on standard CMOS ICs, and reduces noise interference, thereby improving the accuracy and reliability of capacitance measurements.

Implementation Method 1

A method is introduced to compensate for parasitic capacitances by using a current mirror structure to mirror and remove the additional charge added by parasitic capacitances during each charge transfer cycle

Methodology Applied
Scientific EffectCurrent mirror:

Implementation Method 2

The capacitance measurement may be done by repeatedly transferring charge from a capacitor to be measured (C M ) to a reference capacitor (C R )

Methodology Applied
Scientific EffectCharge transfer: Capacitance

Data Source

PatentEP2351220B1Parasitic capacitance cancellation in capacitive measurement applications
Publication Date: 2014.01.01 AZOTEQ PTY LTD
  • EP2351220B1 patent drawingFigure 1~2
  • EP2351220B1 patent drawingFigure 3~4
  • EP2351220B1 patent drawingFigure 5~6

AI summary

An integrated circuit for compensating for parasitic capacitance in a capacitive measuring apparatus wherein a capacitance measurement is done by repeatedly transferring charge from a capacitor to be measured to a reference capacitor.