Capacitive Sense NAND Memory Cell String Architecture
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Solution Overview
Problem
The challenge in fabricating longer strings of series-connected memory cells in NAND memory devices limits memory storage density, as existing industrial techniques face difficulties in successfully constructing these strings.
Innovation Solution
The proposed solution involves innovative array structures and fabrication methods for memory cells, including the use of capacitively coupled sense lines and select gates, which enable the formation of longer strings of series-connected memory cells, enhancing memory storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If common industrial fabrication techniques are used, then manufacturing process is simple, but the number of series-connected memory cells is limited
Solution Approach 1:
The memory array is divided into multiple strings of series-connected memory cells, with each string containing a specific number of cells (e.g., 128, 256, or 512 cells). This segmentation allows the fabrication process to handle manageable units while achieving high overall density through parallel arrays of such strings.
Solution Approach 2:
The patent transitions from planar 2D memory cell arrangements to three-dimensional vertically-aligned memory string structures. Memory cells are stacked vertically along channels extending from the substrate surface, enabling higher cell counts per fabrication unit by utilizing the third dimension (height/depth) rather than only horizontal expansion.
2Productivity
If the number of series-connected memory cells is increased, then memory storage density is improved, but fabrication difficulty increases
Solution Approach 1:
Well structures are formed in the substrate before the memory cell formation process. These pre-formed wells (such as isolation wells or doped regions) establish the foundational structure that guides subsequent memory cell creation, enabling longer strings to be built systematically rather than attempting to create entire long strings in a single complex step.
Solution Approach 2:
Charge trapping layers and tunnel dielectric layers serve as intermediary structures between the substrate and the memory cell control mechanisms. These intermediate layers facilitate the formation process by providing controlled interfaces that enable systematic extension of memory cell strings while maintaining fabrication control.
3Device complexity
If traditional NAND flash memory structures are used, then device complexity is low, but operational efficiency is limited
Solution Approach 1:
The control gate structures serve multiple functions: they control the channel for current flow during read operations, enable charge injection during programming, and facilitate erasure operations. This multi-functionality is achieved through the same basic control gate structure, maintaining relative simplicity while enabling diverse operational modes.
Solution Approach 2:
The memory structure incorporates dynamically controllable elements such as select gates that can be activated or deactivated based on operational requirements. The conductive channels and charge trapping regions can be dynamically charged or discharged to enable different operational states, allowing the same physical structure to adapt to various read, program, and erase operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of longer strings of series-connected memory cells, thereby increasing memory storage density and overcoming the limitations of existing fabrication techniques.
Implementation Method 1
a control gate capacitively coupled to a channel through a gate dielectric
Data Source
AI summary
Memory might include a plurality of series-connected non-volatile memory cells, a plurality of series-connected first field-effect transistors connected in series with the plurality of series-connected non-volatile memory cells, and a second field-effect transistor, wherein the channel of the second field-effect transistor is capacitively coupled to channels of the plurality of series-connected first field-effect transistors. The memory might further include a controller configured to cause the memory to selectively activate a selected non-volatile memory cell, activate each remaining non-volatile memory cell, increase a voltage level of the respective channel of each first field-effect transistor, selectively discharge the voltage level of the respective channel of each first field-effect transistor through the selected non-volatile memory cell, and determine whether the second field-effect transistor is activated in response to a remaining voltage level of the respective channel of each first field-effect transistor.