Capacitive Noise Compensation in Memory Read Bitlines
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Solution Overview
Problem
Existing memory systems face challenges in mitigating noise caused by parasitic Miller capacitors, which affect signal integrity and lead to erroneous readings, especially in memory systems with fewer memory rows like register files.
Innovation Solution
The introduction of additional capacitive noise by coupling a capacitor between the read bitline and the internal inverting node of the read latch helps mitigate the effects of parasitic Miller capacitors, improving signal-to-noise ratio and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If parasitic Miller capacitors are present in the read latch circuit, then the circuit can operate with standard transistor components, but noise is coupled onto the read bitline causing signal integrity degradation and erroneous readings
Solution Approach 1:
The patent introduces an artificial capacitor that deliberately adds capacitive coupling between the read bitline and the inverting node of the read latch. This artificial capacitance is designed to match or exceed the parasitic Miller capacitance, thereby converting the harmful parasitic effect into a beneficial controlled effect that cancels out the noise from the original parasitic capacitor through differential signaling
2Productivity
If the memory system uses a hierarchical bitline arrangement with local and global bitlines, then memory access can be organized efficiently, but noise from parasitic capacitors affects signal integrity particularly in systems with fewer memory rows
Solution Approach 1:
The patent introduces an artificial capacitor as an intermediary element between the read bitline and the inverting node of the read latch. This intermediary component provides controlled capacitive coupling that acts as a mediator to cancel out the noise effects from parasitic Miller capacitors, thereby improving signal integrity without disrupting the hierarchical bitline architecture
3Reliability
If additional capacitive coupling is introduced to mitigate parasitic Miller capacitor noise, then signal-to-noise ratio improves, but circuit complexity increases
Solution Approach 1:
The patent modifies the electrical parameters of the read latch circuit by adding a specifically sized capacitor (artificial Miller capacitor) to change the capacitive coupling characteristics. This parameter change allows the circuit to compensate for parasitic effects without requiring fundamental architectural changes, thereby improving signal-to-noise ratio with minimal increase in complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves a substantial noise reduction, with a 9× improvement in signal-to-noise ratio, while maintaining an acceptable impact on read bandwidth, particularly beneficial in register files with fewer memory rows.
Implementation Method 1
coupling a capacitor between the read bitline and the internal inverting node of the read latch
Data Source
AI summary
A circuit including at least one a bit-storing cell and a read latch coupled to the bit-storing cell via a read bitline includes a capacitive feedback loop between an output of the read latch and the read bitline to inject capacitive noise on the read line that mitigates the effects of a Miller capacitor in the read latch.