Capacitive Output Circuit for High-Voltage Safe Signal Switching
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Solution Overview
Problem
Existing output circuits for semiconductor integrated circuit devices face issues with transistor degradation or damage due to high voltage transitions, as they require transistors to operate within low voltage limits, leading to potential voltage exceedance and increased drain currents.
Innovation Solution
The proposed output circuit design includes p-type and n-type transistors connected in series with capacitors, where the transistors are controlled to be ON or OFF for specific time periods during signal transitions, utilizing capacitors to manage voltage changes and prevent sharp voltage fluctuations, thereby reducing the risk of transistor degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistors are used to output high-voltage signals outside using low-voltage operation, then the output signal amplitude is increased, but the gate-source voltages may exceed withstand voltages and transistor degradation or damage may occur
Solution Approach 1:
The output circuit is divided into multiple transistor stages (first output transistor, second output transistor, third output transistor) with different voltage ratings. Each transistor handles a specific portion of the voltage transition, preventing any single transistor from experiencing voltage exceeding its withstand capability while still achieving high-voltage output capability.
Solution Approach 2:
A capacitor is introduced as an intermediary element between the transistors. This capacitor couples the voltage transitions and helps control the gate-source voltages of the transistors during switching, ensuring that voltage excursions remain within safe limits while enabling high-voltage signal output.
2Reliability
If transistors operate at low voltage to prevent damage, then transistor reliability is improved, but the signal transition speed and output performance are limited
Solution Approach 1:
The voltage transition is segmented across multiple transistor stages with progressively higher voltage ratings. This allows the signal to transition through intermediate voltage levels, enabling faster transitions without subjecting any single low-voltage transistor to excessive stress that would slow down the transition or cause damage.
Solution Approach 2:
The circuit utilizes transistors with different voltage withstand parameters (Vth, Vds(max)) in series configuration. By changing the voltage parameter distribution across the transistor stack, the circuit achieves both fast transition speeds (by allowing higher voltage swings) and maintained reliability (by keeping individual transistor stresses within limits).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively hastens signal transitions while keeping gate-source and drain-source voltages within safe limits, preventing transistor degradation and damage, thus enhancing the durability of semiconductor devices.
Implementation Method 1
a capacitor CP is provided between the gates of the p-type transistors 1 and 2, and a capacitor CN is provided between the gates of the n-type transistors 3 and 4
Data Source
AI summary
An output circuit includes: a first p-type transistor having a source connected to VDDH and a gate to which an input signal is fed; and a second p-type transistor having a source connected to the drain of the first p-type transistor, a drain connected to an output terminal, and a gate connected to a first node. A capacitor has one terminal to which the input signal is fed and the other terminal connected to the first node. A first n-type transistor has a source connected to VDDL, a drain connected to the first node, and a gate to which a signal corresponding to the input signal is fed. A second n-type transistor has a source and a gate both connected to VDDL and a drain connected to the first node.