Capacitive Phase Interpolator for Linear 360° Clock Phase Mixing
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Solution Overview
Problem
Existing phase-interpolator circuits suffer from nonlinearities due to active device usage, leading to increased complexity, area occupation, power consumption, and transistor mismatch, especially in high-frequency applications.
Innovation Solution
A phase-interpolator circuit utilizing a weighting circuit with capacitive impedance values, where the contributions of input signals are based on programmable capacitance ratios, and a biasing circuit provides DC bias and amplification to achieve linear output amplitude across a range of phase values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If active devices are used to sum weighted voltages or currents in phase-interpolator circuits, then the circuit can generate output phases over a 360° range, but nonlinearities occur that limit performance and require increased resolution, resulting in more complicated circuits that occupy more area
Solution Approach 1:
The patent replaces active device-based voltage/current summation with a passive capacitor-based voltage summation system. The capacitor network directly sums the weighted voltages of quadrature clock signals without requiring active buffering or current sources, eliminating the nonlinearities and complexity associated with active devices while maintaining the full 360° phase range capability
Solution Approach 2:
The patent changes the fundamental operating parameter from active current/voltage control to passive capacitive weighting. By using capacitor ratios to determine phase interpolation weights instead of active device control, the system achieves linear operation across the full phase range without requiring increased resolution or more complex circuitry
2Measurement precision
If increased resolution is used to minimize phase steps and reduce differential nonlinearity, then phase interpolation accuracy improves, but the circuit becomes more complicated and occupies more area
Solution Approach 1:
The patent eliminates the need for high-resolution active device control by using passive capacitor networks that inherently provide linear voltage summation. The capacitor ratios directly determine phase weights without requiring fine-resolution control, achieving accurate phase interpolation with simpler, smaller circuitry
Solution Approach 2:
The patent uses multiple copies of the same capacitor network structure for different phase interpolations rather than using progressively more complex active device arrangements. This modular capacitor-based approach achieves the required precision without increasing overall circuit area or complexity
3Productivity
If current sources are used with finite output impedance in phase-interpolator circuits, then the circuit can provide current proportional to input clock signals, but the weight-change technique becomes nonlinear because the current changes nonlinearly even when device dimensions are changed linearly
Solution Approach 1:
The patent replaces active current sources with finite output impedance with passive capacitor-based voltage summation. The capacitor network directly weights and sums the voltages of quadrature clock signals without requiring current sources, eliminating the nonlinear current changes that occur when device dimensions are adjusted and providing inherently linear operation
Solution Approach 2:
The patent changes the control mechanism from active current modulation to passive capacitive voltage division. By using capacitor ratios to determine weightings instead of adjusting current source dimensions, the system achieves linear weight changes that directly proportional to the capacitor ratio adjustments, eliminating the nonlinearities inherent in active current source operation
4Adaptability or versatility
If gate-drain capacitance is present in phase-interpolator circuits, then the circuit can provide alternative paths for clock signals, but capacitive feed-through occurs that is worse in high-frequency applications where the gate-drain capacitance provides a lower impedance path
Solution Approach 1:
The patent replaces active device-based signal routing with passive capacitor-based voltage summation. The capacitor network directly combines the voltages of quadrature clock signals without requiring active switching or buffering, eliminating the gate-drain capacitance feed-through paths that plague active device implementations and providing inherently clean signal operation across all frequencies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces nonlinearity, capacitance, and layout area while minimizing power consumption and transistor mismatch, resulting in improved linearity and reduced phase-step variations compared to existing circuits.
Implementation Method 1
a weighting circuit with an output and inputs electrically coupled to the first and second input nodes, wherein contributions of the first and second clock phases, respectively, to the output are weighted based on associated first and second impedance values in the weighting circuit
Data Source
AI summary
A phase-interpolator circuit is described. In the phase-interpolator circuit, an output signal, having a fundamental frequency and a phase, is generated based on a weighted summation of a first reference signal and a second reference signal, where the first reference signal has the fundamental frequency and a first phase, and the second reference signal has the same fundamental frequency and a second phase. Note that contributions of the first reference signal and the second reference signal, respectively, to the output signal are determined based on associated first and second impedance values in a weighting circuit in the phase-interpolator circuit. For example, a programmable capacitance ratio of two capacitors may be used to interpolate between the first reference signal and the second reference signal. Additionally, the phase-interpolator circuit may include a biasing circuit that provides a DC bias to the weighting circuit, and which amplifies the output of the weighting circuit to provide the output signal.