Capacitive Contact Plug Barrier Layer to Prevent Over-Etching
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Solution Overview
Problem
In existing semiconductor structures, the capacitive structure is prone to over etching when in contact with a landing pad, leading to the formation of holes and potential short circuits between the upper and lower electrodes due to poor adhesion of high-K materials.
Innovation Solution
A method for processing a capacitive structure involves forming a barrier layer on a substrate with a landing pad, etching the barrier layer to expose part of the landing pad, and then forming a first dielectric layer covering the landing pad and barrier layer, followed by etching to create a capacitive contact plug.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the capacitive structure is directly formed on the landing pad, then the manufacturing process is simple, but over etching occurs leading to hole formation and potential short circuits
Solution Approach 1:
The patent applies preliminary action by forming a barrier layer on the landing pad before forming the capacitive structure. This barrier layer is etched partially to expose a portion of the landing pad, creating a controlled interface that prevents over-etching damage while maintaining manufacturing feasibility. The preliminary preparation of the landing pad surface ensures reliable capacitive structure formation without direct contact between the high-K material and the entire landing pad surface.
Solution Approach 2:
The patent introduces an intermediary approach by using the barrier layer as a mediating structure between the landing pad and the capacitive structure. The barrier layer is selectively etched to create a controlled exposure of the landing pad, serving as an intermediate step that prevents direct harmful interaction (over-etching) while enabling the desired electrical connection. This intermediary structure resolves the contradiction by providing both protection and controlled contact.
2Reliability
If high-K material is used in the capacitive structure, then the dielectric performance is improved, but adhesion to the electrode material is poor causing short circuits
Solution Approach 1:
The patent applies local quality by creating different adhesion conditions in different areas. The barrier layer provides good adhesion to the electrode material (TiN) in areas where it remains, while the selectively etched portions expose the landing pad for controlled contact. This local differentiation of material properties and interfaces ensures both the dielectric performance of the high-K material and adequate adhesion strength, preventing short circuits while maintaining electrical functionality.
Data Source
AI summary
The disclosure provides a method for processing a capacitive structure, and a semiconductor structure. The method for processing the capacitive structure includes the following steps: providing a substrate, forming a landing pad on a surface of the substrate, and etching the landing pad; forming a barrier layer on the surface of the substrate, the barrier layer covering the landing pad; etching the barrier layer to expose a part of the landing pad; forming a first dielectric layer on the surface of the substrate, the first dielectric layer covering the landing pad and the barrier layer; and etching the first dielectric layer and forming a capacitive contact plug.