Capacitive Pressure Sensor Membrane Fabrication
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Solution Overview
Problem
Piezo resistive pressure sensors face challenges due to large deflections and temperature variations, which induce non-linearity, and cannot be integrated on top of CMOS devices due to the deposition temperature limitations of crystalline silicon materials, leading to increased footprint and cost in dual die package solutions.
Innovation Solution
A method for forming a suspended membrane using tungsten, which allows for the fabrication of capacitive pressure sensors on top of integrated circuits using standard CMOS fabrication techniques, reducing the footprint and stress sensitivity, and utilizing adhesive layers to improve adhesion and reduce stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If piezo resistive pressure sensors are used, then pressure measurement is achieved, but large deflections and temperature variations induce non-linearity
Solution Approach 1:
The patent replaces the piezo resistive readout mechanism with a capacitive sensing mechanism. Instead of measuring resistance changes in silicon membranes under stress, the invention uses capacitive sensors that measure pressure through changes in capacitance, eliminating the non-linearity issues inherent in piezo resistive materials while maintaining pressure measurement functionality
Solution Approach 2:
The invention changes the fundamental measurement parameter from electrical resistance (piezo resistive) to electrical capacitance. This parameter change allows for linear pressure measurement across a wide range of temperatures and pressures, as capacitive sensing does not suffer from the same non-linear thermal and mechanical effects that plague piezo resistive sensors
2Ease of manufacture
If piezo resistive materials are used, then pressure sensing is enabled, but integration on top of CMOS devices is not possible due to deposition temperature limitations
Solution Approach 1:
The invention changes the material deposition temperature parameter from high temperature (required for crystalline silicon piezo resistive materials) to low temperature (compatible with CMOS processes). By using amorphous silicon or other low-temperature compatible materials, the patent enables direct integration of pressure sensors on top of CMOS devices using standard fabrication techniques
Solution Approach 2:
The invention extracts the pressure-sensitive membrane function from the CMOS process constraints. By separating the membrane material requirements from the CMOS compatibility requirements, the patent allows the membrane to be formed independently at low temperatures using techniques such as sputtering or CVD, then integrated onto the CMOS device without requiring high-temperature crystalline silicon deposition
3Reliability
If tungsten is used for the suspended membrane, then the membrane is inert to HF vapor and has low coefficient of thermal expansion, but high stress may lead to failure during etching
Solution Approach 1:
The patent applies preliminary stress-relief actions before the critical etching step. This includes forming the tungsten membrane with controlled residual stress, using stress-compensating layer structures, and optimizing the membrane geometry to distribute stresses evenly. These preliminary measures prevent stress-induced failure during the subsequent sacrificial layer removal process
Solution Approach 2:
The invention uses composite material structures to mitigate tungsten's high stress. By combining tungsten with other materials having different stress characteristics (such as silicon nitride or oxide layers), the patent creates a composite membrane system where the overall stress is balanced, maintaining both HF resistance and structural integrity during processing
4Ease of manufacture
If a dual die package solution is used, then capacitive pressure sensors can be formed on top of integrated circuits, but the footprint and cost increase
Solution Approach 1:
The patent merges the pressure sensor die and the readout circuit die into a single integrated device. By enabling direct integration of capacitive pressure sensors on top of CMOS readout circuits using low-temperature compatible materials and processes, the invention eliminates the need for separate dies and interconnect structures, thereby reducing the overall footprint and manufacturing cost while maintaining full functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate and repeatable pressure readings over a range of temperatures and pressures, reduces the device footprint, and integrates capacitive pressure sensors on a single die, improving sensitivity and power consumption while minimizing stress and temperature sensitivity.
Implementation Method 1
The first electrically conductive material may be deposited by physical vapor deposition
Implementation Method 2
The sacrificial layer may be removed by HF vapor that will not attack the tungsten membrane during etching of the sacrificial layer
Data Source
Figure 1~2
Figure 3A~3B
Figure 3C~3D
AI summary
Embodiments of a method for forming a suspended membrane include depositing a first electrically conductive material above a sacrificial layer and within a boundary trench. The first electrically conductive material forms a corner transition portion above the boundary trench. The method further includes removing a portion of the first electrically conductive material that removes at least a portion of uneven topography of the first electrically conductive material. The method further includes depositing a second electrically conductive material. The second electrically conductive material extends beyond the boundary trench. The method further includes removing the sacrificial layer through etch openings and forming a cavity below the second electrically conductive material. The first electrically conductive material defines a portion of a sidewall boundary of the cavity.