Capacitive Sensor Readout Circuit With Low-Power Single-Phase Sampling

The patent implements periodic action by using a single-phase sampling approach where the sensor is sampled once per clock cycle instead of multiple times. The capacitive sensor is charged during the clock high period and the sampled value is captured during the clock low period, creating a periodic measurement rhythm that reduces power consumption while maintaining acceptable responsiveness through the efficient use of each sampling period.

The patent replaces the conventional multi-phase analog signal processing mechanism with a simplified single-phase sampling mechanism. Instead of using complex analog circuitry with multiple sampling phases and operational amplifiers, the invention uses a straightforward charge-and-sample approach controlled by a single clock signal, substituting mechanical/analog complexity with a cleaner electrical control scheme that reduces power consumption while preserving sensitivity.

The patent extracts and eliminates the unnecessary ring oscillator and counter components from the conventional measurement system. By directly sampling the capacitive sensor output with a simple clocked circuit, the invention removes the overhead of generating high-frequency clock signals and counting operations, keeping only the essential sampling function that directly measures capacitive changes without the power-consuming auxiliary mechanisms.

The patent employs a simplified measurement approach that uses basic digital logic components instead of expensive and power-hungry operational amplifiers. The solution uses simple clocked switches and latches to capture charge transfer information, replacing complex analog processing with straightforward digital sampling that consumes significantly less power while achieving the same measurement objective.