Capacitive SAR ADC Switching Scheme for Lower Capacitance
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Solution Overview
Problem
Capacitive successive approximation analog-to-digital converters (SAR ADCs) require a large number of capacitors and total capacitance to achieve high accuracy, leading to increased manufacturing costs and complexity.
Innovation Solution
A capacitive SAR ADC design using two arrays of N capacitors each, with specific voltage generation and switch control mechanisms, allowing for the reduction of total capacitance and capacitor count while maintaining N-bit binary code output accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If two capacitor arrays consisting of N+1 capacitors are used to achieve N-bit binary code output accuracy, then measurement precision is improved, but device complexity and quantity of components increase
Solution Approach 1:
The patent merges two separate capacitor arrays into a single shared capacitor array where capacitors are reused for both differential signal paths. The same capacitor array serves both the positive and negative differential inputs, reducing the total capacitor count from 2(N+1) to N+1 while maintaining N-bit accuracy through differential comparison architecture.
Solution Approach 2:
Each capacitor in the shared array performs multiple functions: it participates in both differential signal paths and can be selectively connected to different nodes (positive terminal, negative terminal, or virtual ground) based on the successive approximation algorithm stage. This multi-functionality allows a single capacitor array to replace what would traditionally require two separate arrays.
2Measurement precision
If two capacitor arrays consisting of N+1 capacitors are used to achieve N-bit binary code output accuracy, then measurement precision is improved, but manufacturing cost increases
Solution Approach 1:
By merging two capacitor arrays into one shared array, the patent reduces the total component count by approximately 50%, directly lowering manufacturing costs. The shared capacitor array is controlled through switch matrices that route capacitors to appropriate nodes, achieving the same N-bit accuracy with fewer physical components requiring fabrication, testing, and assembly.
3Measurement precision
If two capacitor arrays consisting of N+1 capacitors are used to achieve N-bit binary code output accuracy, then measurement precision is improved, but total capacitance increases
Solution Approach 1:
The patent combines two capacitor arrays into a single shared array, reducing the total capacitance sum from 2×(N+1)C to (N+1)C where C is the unit capacitance. The differential architecture ensures that the same capacitance value provides the necessary resolution for N-bit conversion by comparing differential voltages rather than requiring doubled capacitance resources.
Data Source
AI summary
A capacitive successive approximation analog-to-digital converter is provided, where the capacitive successive approximation analog-to-digital converter includes a first capacitor array including N first capacitors; a second capacitor array including N second capacitors; a voltage generation circuit configured to generate a common mode voltage, a reference voltage, a first voltage and a second voltage; a first switch, a second switch, N third switches and N fourth switches; a comparator including a first input end, a second input end and an output end, where upper plates of the N first capacitors are connected to the first input end and upper plates of the N second capacitors are connected to the second input end; and a successive approximation logic controller connected to the output end of the comparator. The capacitive successive approximation analog-to-digital converter in the above technical solution can use 2N capacitors to implement outputting an N-bit binary code.