Capacitive Sense NAND Memory Array Structures for High Density
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Solution Overview
Problem
The challenge in NAND flash memory technology is the practical limit on the number of series-connected memory cells due to difficulties in fabricating longer strings, which restricts memory storage density.
Innovation Solution
The development of advanced memory array structures and sense line configurations that enable longer strings of series-connected memory cells by optimizing the arrangement of select gates, capacitances, and data lines, allowing for improved connectivity and operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If common industrial fabrication techniques are used, then manufacturing simplicity is maintained, but the number of series-connected memory cells is limited
Solution Approach 1:
The memory array is divided into multiple strings of series-connected memory cells, with each string containing a manageable number of cells (e.g., 64 cells per string). This segmentation allows standard fabrication techniques to be applied to each individual string while achieving high overall storage density through the parallel arrangement of multiple strings.
Solution Approach 2:
The patent transitions from planar memory cell arrangements to three-dimensional vertically-stacked memory cell structures. By stacking memory cells vertically in multiple layers, the system increases the number of series-connected cells along the vertical dimension while maintaining compatibility with existing fabrication processes.
2Quantity of substance
If longer strings of series-connected memory cells are implemented, then memory storage density increases, but fabrication challenges increase
Solution Approach 1:
Rather than creating excessively long single strings that would require ultra-precise fabrication, the memory array is segmented into multiple parallel strings of moderate length. Each string maintains a practical cell count (e.g., 64 cells) that can be fabricated with existing precision, while the aggregate storage density is achieved through the parallel configuration of many such strings.
Solution Approach 2:
The patent applies different structural configurations to different regions of the memory array, optimizing local cell arrangements and string lengths to match fabrication capabilities while maximizing overall density. Select gates and capacitance structures are locally optimized to ensure reliable operation of each string segment.
Data Source
AI summary
Arrays of memory cells might include a first upper data line, a second upper data line, a lower data line, a first pass gate selectively connected to the lower data line, a second pass gate connected to the first pass gate and selectively connected to the lower data line, a third pass gate selectively connected to the lower data line, a fourth pass gate connected to the third pass gate and selectively connected to the lower data line, unit column structures selectively connected to a respective one of the upper data lines and capacitively coupled to a first channel of a respective one of the pass gates, and control lines capacitively coupled to a second channel of a respective one of the pass gates.