Capacitive Sensing for IC Authentication and Tamper Detection
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Solution Overview
Problem
Conventional methods for hardware security in Integrated Circuits (ICs) fail to authenticate the origin of die fabrication and detect tampering effectively, relying on costly coatings or impractical differential capacitance measurements that do not provide traceability or reliable authentication.
Innovation Solution
The method involves high-resolution measurement of on-chip capacitance values and Resistor-Capacitor (RC) time constants to authenticate the die's origin and detect tampering, using self-reported results from the die to determine authenticity and identify unique unclonable values, without additional coatings or encapsulation steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If expensive protective top layer coatings with randomly distributed conductive particles are used to encapsulate the die, then tamper detection capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the identification and authentication functionality from the expensive protective coating approach and implements it using standard BEOL metallization layers that already exist in the IC fabrication process. By measuring capacitances formed by the existing metal interconnect structure without requiring additional protective coatings, the solution eliminates the need for expensive specialized materials while maintaining tamper detection capability.
Solution Approach 2:
The patent makes the standard BEOL metallization layers serve multiple functions: they continue to provide their primary function as electrical interconnects while simultaneously forming capacitive structures for identification, authentication, and tamper detection. This multi-functionality eliminates the need for separate expensive protective coatings with conductive particles, as the existing metal layers are repurposed for security functions.
2Measurement precision
If single-bit differential measurement of capacitances is used with special layout of metal lines, then identification capability is improved, but area overhead increases significantly
Solution Approach 1:
The patent uses the existing BEOL metallization layers for dual purposes: maintaining their primary function as electrical interconnects while simultaneously serving as the capacitive sensing structure for identification. By measuring capacitances at multiple nodes across the existing metal interconnect network, the solution achieves high-resolution identification without requiring dedicated sensing metal lines or special layouts that would consume additional area.
Solution Approach 2:
The patent transitions from single-bit differential measurement to high-resolution multi-bit capacitance measurements by utilizing the inherent capacitance variations in the standard metal interconnect structure. By measuring multiple capacitance values at different nodes and combining them through digital processing, the system achieves high identification precision without requiring specialized measurement circuitry or additional routing area.
3Measurement precision
If conventional identification methods like PUFs are used to provide unique serial numbers, then die differentiation is improved, but traceability to fabrication origin is lost
Solution Approach 1:
The patent replaces conventional PUF approaches that rely on random physical variations during fabrication with a system based on measuring capacitances of the deterministic BEOL metallization structure. The capacitance values are determined by the controlled metal interconnect geometry and materials specified in the design, which are then fabricated with process-specific characteristics. This substitution enables both unique identification and traceability to the fabrication origin, as the capacitance measurements reflect both the design intent and the specific manufacturing process used.
4Reliability
If high-resolution measurement of on-chip capacitance values and RC time constants is performed, then authentication accuracy and tamper detection are improved, but measurement complexity increases
Solution Approach 1:
The patent implements self-service by integrating the capacitance and RC time constant measurement functionality directly into the IC device itself. The device contains internal circuitry that automatically measures its own BEOL metallization capacitances and RC time constants without requiring external measurement equipment. This self-measurement capability simplifies the overall system complexity while enabling high-resolution authentication and tamper detection, as the device performs the measurements autonomously using its existing power and logic resources.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides direct and accurate authentication and tamper detection, ensuring the die's origin is verified and tampering is detected with high certainty, reducing costs and overhead, and offering unique identification for each die.
Implementation Method 1
performing self-testing of at least one of an on-die capacitance or an RC time constant on a die of the IC to generate self-reported results
Data Source
AI summary
Systems and methods are provided for Integrated Circuit (IC) identification, authentication, and tamper detection. Die identification, authentication, and tamper detection techniques are described that employ capacitive sensing of on-chip interconnect. The signal and power routing in ICs have nominal capacitance values that are characteristic of their foundry, and the variance of these values, due to process tolerances, is unique to each device. Measuring these capacitances provides not only support for determining the authenticity of the device and fabrication site, but also provides distinct identification of each part. By integrating Capacitance-to-Digital Converters (CDCs) with low power and area overhead, capacitance values from intrinsic functional nets can be reported, and the need for separate additive test circuitry can be avoided.