Capacitive Sensor Alignment for 3D Chip Stacking
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Solution Overview
Problem
Existing alignment measurement systems for 3D chip stacking require expensive and complex components, limiting their accessibility and precision in achieving sub-micron alignment.
Innovation Solution
An alignment measurement system utilizing integrated CMOS capacitive sensors and sensing circuits to provide on-chip measurement along vertical Z-axis or lateral X/Y-axis, eliminating the need for costly components by using a multiple-capacitor structure and differential amplifiers to detect misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If expensive and complex servomechanisms, sensors and actuators are used, then alignment measurement precision can be improved, but device complexity and cost increase
Solution Approach 1:
The patent replaces complex mechanical servomechanisms and actuators with a purely electronic measurement system using capacitive sensors and signal processing circuits. The alignment measurement is achieved through electrical field interactions between capacitive elements rather than mechanical scanning or positioning mechanisms, thereby eliminating mechanical complexity while maintaining sub-micron precision
Solution Approach 2:
The patent uses capacitive coupling to create an electrical field copy or representation of the physical alignment state. By measuring capacitance values between stacked chips, the system creates an electrical model of the mechanical positioning accuracy, allowing precise measurement without direct mechanical contact or complex physical sensors
2Measurement precision
If expensive and complex servomechanisms, sensors and actuators are used, then alignment measurement precision can be improved, but manufacturing cost increases
Solution Approach 1:
The patent employs standard CMOS capacitive sensors and off-the-shelf operational amplifiers that can be mass-produced using conventional semiconductor fabrication processes. These inexpensive electronic components replace expensive specialized alignment equipment, making high-precision measurement economically viable for commercial 3D stacking applications
Solution Approach 2:
The capacitive sensor structure serves multiple functions: it acts as both the primary sensing element for alignment measurement and as part of the inter-chip electrical connection system. This multi-functionality eliminates the need for separate dedicated alignment sensors, reducing overall component count and manufacturing complexity
3Ease of operation
If standard alignment systems are used, then ease of implementation is improved, but measurement precision for sub-micron alignment deteriorates
Solution Approach 1:
The patent achieves sub-micron precision by measuring changes in capacitance parameters that occur with sub-micron displacements between stacked chips. The system translates mechanical position variations into electrical capacitance variations through the capacitive coupling mechanism, enabling high-precision measurement that standard systems cannot achieve
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise sub-micron alignment measurements without expensive components, enhancing the accuracy and reproducibility of chip positioning in 3D stacking configurations.
Implementation Method 1
An embodiment of the present invention associates with at least an integrated CMOS capacitive sensor connected to the chips comprised in a three-dimensional (3D) stacking configuration a sensing circuit to provide an on-chip measurement of a stacked configuration alignment
Data Source
AI summary
An embodiment of the present invention relates to a alignment measurement system for measuring alignment between a plurality of chips of a device, the chips being assembled in a three-dimensional stacking configuration and equipped with at least an integrated capacitive sensor, including a multiple-capacitor structure integrated in the capacitive sensor, at least a sensing circuit connected to the multiple-capacitor structure which issues an output voltage, proportional to a variation of a capacitive value of the multiple-capacitor structure of the integrated capacitive sensor of the device and corresponding to a measured misalignment between the chips of the device.