Capacitive Sensor Chip With Dynamic Charge-Domain Amplifier Array
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional capacitive sensor chips face challenges in achieving high energy efficiency, high precision, and large dynamic range while maintaining energy efficiency, especially in ultra-low-power IoT scenarios, due to limitations in conversion resolution, energy consumption, and redundancy in existing technologies.
Innovation Solution
A capacitive sensor chip based on a zoom architecture with two stages for quantization, using a successive approximation register (SAR) for coarse quantization and a delta-sigma modulator for fine quantization, powered by a floating capacitor and a power-aware module to control power consumption, featuring a dynamic charge-domain amplifier array with an inverter amplifier and adaptive power allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If SAR-based CDC is used for capacitive conversion, then energy efficiency is improved, but conversion resolution deteriorates
Solution Approach 1:
The capacitive conversion process is divided into two separate stages: a first stage for coarse quantization using SAR-based CDC and a second stage for fine quantization using delta-sigma modulator. This segmentation allows each stage to be optimized for its specific function, with the SAR stage providing energy-efficient coarse conversion and the delta-sigma stage delivering high-resolution fine conversion, thereby resolving the contradiction between energy efficiency and conversion resolution.
2Measurement precision
If delta-sigma modulator is used for high conversion resolution, then measurement precision is improved, but energy consumption increases
Solution Approach 1:
The system segments the quantization task into two stages, with the delta-sigma modulator handling only fine quantization of the residual signal after coarse conversion. This reduces the overall complexity and energy consumption compared to using a full-resolution delta-sigma modulator, while still achieving high conversion resolution through the combination of both stages.
Solution Approach 2:
The patent employs dynamic element matching (DEM) technique in the capacitor array of the delta-sigma modulator, which dynamically swaps capacitor positions to randomize quantization errors and improve linearity. This dynamic approach enhances measurement precision without requiring excessive energy consumption, as it uses simple switching operations rather than high-power analog circuits.
3Measurement precision
If FLL-based CDC is used for high accuracy, then measurement precision is improved, but energy consumption increases
Solution Approach 1:
The patent replaces the continuous feedback mechanism of FLL-based CDC with a discrete two-stage quantization approach. Instead of using an active filter and bias circuits that consume large amounts of power in FLL, the invention uses a SAR-based coarse quantization stage followed by a delta-sigma fine quantization stage, achieving high accuracy through digital processing rather than power-intensive analog feedback circuits.
4Adaptability or versatility
If zoom-based CDC is used for large dynamic range, then adaptability is improved, but energy efficiency deteriorates
Solution Approach 1:
The zoom-based CDC is implemented through segmentation into two stages: SAR-based coarse quantization that handles large signal variations and delta-sigma fine quantization that provides high resolution. This segmented approach achieves large dynamic range adaptability without the energy inefficiency of traditional single-stage zoom circuits, as each stage operates in its optimal efficiency range.
Data Source
AI summary
Disclosed is a capacitive sensor chip based on a power-aware dynamic charge-domain amplifier array. The capacitive sensor chip is based on a zoom architecture and includes: an architecture having two or more stages for capacitive quantization in which a first stage performs coarse quantization using a successive approximation register (SAR) and a second stage performs fine quantization using a delta-sigma modulator, an amplifier in the capacitive sensor chip is powered by a floating capacitor, the floating capacitor is connected to a power supply to being charged and connected to the amplifier to power the amplifier by controlling switches; a first-order integrator of the delta-sigma modulator includes an amplifier array having a scale of N bits and 2N amplifiers where N is a positive integer. By the capacitive sensor chip based on the power-aware dynamic charge-domain amplifier array, utilization efficiency of charges can be effectively improved, power consumption overheads nay be effectively saved, energy efficiency of a system is greatly improved and a driving capability of the subsequent-stage amplifier may be adaptively distributed according to the size of an input capacitance.