Capacitive Sensor Stackup with Metal Interconnect Routing
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Solution Overview
Problem
Capacitive sensing devices face challenges with high resistivity and slow response times, particularly in larger input devices, where transparent conducting oxides like ITO are undesirable due to visibility issues and performance limitations.
Innovation Solution
A multi-layered sensing stack is implemented with a metal interconnect layer having lower resistivity than the conductive sensor layer, where routing traces are masked or shielded to prevent visibility and enhance response times, using materials like aluminum or copper for improved signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If transparent conducting oxides like ITO are used in the conductive sensor layer, then visibility is maintained, but response time increases and resistivity increases
Solution Approach 1:
The patent divides the conductive layer into two separate layers: a transparent conducting oxide layer (ITO) for visibility and a metal interconnect layer for low-resistivity signal routing. This segmentation allows each layer to optimize its specific function without compromise.
Solution Approach 2:
The patent adds a vertical dimension by stacking the metal interconnect layer beneath the transparent conducting oxide layer. This multi-layer arrangement allows the metal traces to route signals without compromising the visual transparency of the top layer.
2Loss of time
If metal interconnect layer is used for routing traces, then resistivity decreases and response time improves, but visual artifacts may be created
Solution Approach 1:
The patent extracts the signal routing function from the visible transparent conducting oxide layer and places it in the underlying metal interconnect layer. This separation removes the source of visual artifacts from the visible path while maintaining electrical functionality.
Solution Approach 2:
The transparent conducting oxide layer acts as an intermediary that maintains visual transparency while the metal layer beneath handles the electrical signal routing. The TCO mediates between the need for visibility and the need for low-resistivity routing.
3Area of stationary object
If larger input devices are used, then sensing area increases, but response time worsens due to higher resistivity
Solution Approach 1:
The patent segments the conductive path into two functional layers, allowing the metal interconnect layer to provide low-resistivity routing across the entire sensing area while the TCO layer maintains transparency. This enables large sensing areas without the resistivity penalties that would normally slow response time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables faster response times and shorter settling times without creating visual artifacts, improving the performance of capacitive sensing devices while maintaining a sleek design.
Implementation Method 1
The metal interconnect layer is fabricated from a material having a resistivity lower than a material comprising the conductive sensor layer
Implementation Method 2
The routing traces are coupled to the plurality of sensor electrodes and extend from within a first region defined by the areal extent of the plurality of sensor electrodes to a second region outward of the areal extent of the plurality of sensor electrodes
Data Source
AI summary
Capacitive sensing devices that provide short settling time and fast response without creating undesirable visual effects are disclosed herein. In one embodiment, the capacitive sensing device includes a pixel layer stacked with a conductive sensor layer and a metal interconnect layer. The conductive sensor layer has a plurality of sensor electrodes, each of which includes one or more common electrodes. The plurality of sensor electrodes has an areal extent in which an active area of the sensor electrodes is configured to detect input events. The metal interconnect layer is disposed in the active area and includes routing traces. The routing traces are coupled to the plurality of sensor electrodes and extend from within a first region defined by the areal extent of the plurality of sensor electrodes to a second region outward of the areal extent of the plurality of sensor electrodes.