Capacitive-Coupled Non-Volatile TFT Strings for 3D Memory Arrays
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Solution Overview
Problem
Conventional high-density memory structures, such as NAND and NOR strings, face limitations in read-latency, program-disturb, and power dissipation, with NAND strings having high series resistance and NOR strings requiring large electron currents for programming, which restricts the number of transistors that can be programmed in parallel.
Innovation Solution
The implementation of NOR strings with TFTs organized in horizontal active strips and vertical local word lines, allowing for pre-charging of unselected TFTs to reduce read-latency and power dissipation, and enabling massively parallel read, write, or erase operations by using the strip capacitor as a virtual reference voltage source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND strings with series-connected TFTs are used to achieve high-density storage, then storage capacity increases, but read-latency increases and power dissipation increases due to high series resistance
Solution Approach 1:
The memory array is segmented into multiple independent NOR strings, each capable of parallel operation. This segmentation allows simultaneous read operations across multiple strings, reducing overall read-latency while maintaining high storage capacity through increased parallelism
Solution Approach 2:
The patent transitions from planar memory organization to three-dimensional stacked architecture with vertical control gates. This dimensional change enables higher storage density without increasing the number of TFTs in series, thereby reducing read-latency and power dissipation associated with long series chains
2Loss of time
If NOR strings with parallel-connected TFTs are used to reduce read-latency, then read speed improves, but program-disturb conditions worsen due to large electron currents required for programming
Solution Approach 1:
The patent applies different quality characteristics to different parts of the memory structure: vertical control gates provide localized, precise control over electron injection into charge-trapping layers, enabling efficient programming with reduced currents. This localized control quality reduces program-disturb effects while maintaining the parallel NOR string architecture's fast read performance
Solution Approach 2:
The invention changes the programming mechanism parameters by using Fowler-Nordheim tunneling or direct tunneling instead of channel hot-electron injection. This parameter change reduces the electron current required for programming by orders of magnitude, eliminating program-disturb conditions while preserving the low read-latency benefit of parallel NOR string architecture
3Ease of manufacture
If polysilicon thin-film TFTs are used to form high-density arrays, then manufacturing ease improves, but channel mobility decreases leading to higher resistivity
Solution Approach 1:
The patent employs composite material structures for TFT channels, combining polysilicon with crystalline seed layers or using semiconductor-salt techniques to induce crystal formation. This composite approach maintains the ease of polysilicon deposition while dramatically improving channel mobility through crystalline structure formation, achieving both manufacturing ease and high reliability
4Quantity of substance
If the number of TFTs in a NAND string is increased to boost storage capacity, then storage density improves, but series resistance increases limiting further scaling
Solution Approach 1:
The patent implements three-dimensional stacked memory architecture with multiple horizontal active strips controlled by vertical gates. This dimensional transition allows storage density to increase vertically through stacking rather than horizontally through longer series chains, effectively decoupling storage density from series resistance and enabling continued scaling without the energy loss constraints of planar NAND strings
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces read-latency to levels approaching dynamic random access memory (DRAM), decreases sensitivity to disturb conditions, lowers cost-per-bit, and increases data throughput by allowing concurrent operations on multiple active strips.
Implementation Method 1
the strip capacitor as a virtual reference voltage source
Data Source
AI summary
Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.