Capacitive Elements in Trenches for High Density IC Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Capacitive elements in integrated circuits are bulky and require numerous expensive fabrication steps, making it challenging to increase capacitance per unit area and implement these steps concurrently with other integrated circuit components.
Innovation Solution
A process involving directional etching in semiconductor substrates to form sacrificial trench isolations and electrode trenches, filled with dielectric and conductive materials respectively, allowing for increased electrode area without additional steps or substrate real estate occupancy, while being integrated with conventional integrated circuit fabrication techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional fabrication steps are used for capacitive elements, then the capacitance per unit area is limited, but the fabrication process becomes bulky and requires numerous expensive steps
Solution Approach 1:
The patent merges the fabrication of capacitive elements with standard integrated circuit fabrication processes. The capacitive elements are formed using the same trench isolation and electrode deposition steps that are already performed for transistor fabrication, eliminating dedicated fabrication steps and reducing overall process complexity.
Solution Approach 2:
The fabrication process is designed to be universal, serving multiple functions: forming shallow trench isolations for transistor isolation, creating electrode trenches for capacitive elements, and depositing electrodes and dielectric layers all within the same process sequence used for standard CMOS fabrication.
2Quantity of substance
If dedicated fabrication steps are implemented for capacitive elements, then capacitance can be increased, but substrate space occupancy increases
Solution Approach 1:
The patent transitions from planar capacitance to three-dimensional capacitance by forming electrode trenches that extend vertically into the substrate. The capacitive structure utilizes the depth dimension (extending to the buried layer) in addition to the surface area, thereby increasing capacitance without proportionally increasing the footprint on the substrate surface.
Solution Approach 2:
The capacitive element structure is nested within the existing integrated circuit architecture. The electrode trenches are formed within the substrate depth, utilizing the vertical space between the surface and the buried layer, effectively nesting the capacitive volume within the substrate thickness rather than requiring additional lateral space.
3Quantity of substance
If capacitive elements are fabricated with larger electrode area, then capacitance increases, but fabrication steps and cost increase
Solution Approach 1:
The fabrication steps for capacitive elements are merged with standard IC fabrication processes including shallow trench isolation formation, electrode deposition, and dielectric layer deposition. This integration means that the same equipment, materials, and process parameters are used, eliminating the need for additional dedicated fabrication steps and reducing manufacturing cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enhances capacitance per unit area of capacitive elements without increasing fabrication complexity or substrate space, enabling their concurrent production with other integrated circuit components.
Implementation Method 1
a directional etch that is configured to etch the semiconductor substrate, the directional etch being aligned with said at least one sacrificial trench isolation and continuing depthwise to a portion of the substrate which is located under said at least one sacrificial trench isolation
Data Source
AI summary
A capacitive element is fabricated by forming a sacrificial trench isolation and directionally etching through the sacrificial trench isolation and into an underlying semiconductor substrate to form an electrode trench. The electrode trench is then clad with an insulating material and filled with a conductive material. The conductive fill provided one capacitor electrode and the semiconductor substrate forms another capacitor electrode, with the insulating material cladding forming the capacitor dielectric layer.