Capacitive Voltage Dividers for Memory Power Management
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Solution Overview
Problem
Existing memory sub-systems, such as solid-state drives (SSDs), face challenges in achieving high energy efficiency, particularly in low power modes where linear and switching voltage regulators require minimum operational voltages and currents, leading to reduced energy efficiency when translating input voltages to output voltages with significant differentials.
Innovation Solution
The implementation of a capacitive voltage divider (CVD) selectably coupled to either a linear voltage regulator (LVR) or a switching voltage regulator (SVR), allowing for conversion of primary supply voltages to a second supply voltage within a compatible range for the LVR or SVR, thereby reducing input-output voltage differentials and enhancing energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If linear voltage regulators or switching voltage regulators are used to translate input voltages to output voltages with significant differentials, then voltage regulation is achieved, but energy efficiency deteriorates due to minimum operational voltages and currents requirements
Solution Approach 1:
The voltage translation process is segmented into two stages: first, a capacitive voltage divider performs initial voltage reduction to bring the input voltage into a compatible range, and second, a linear or switching voltage regulator performs fine regulation. This segmentation allows the regulator to operate efficiently without requiring high minimum voltages, thereby improving energy efficiency.
Solution Approach 2:
The capacitive voltage divider acts as an intermediary component between the input voltage source and the voltage regulator. It pre-processes the input voltage by reducing it to a compatible range, enabling the regulator to operate in its optimal efficiency range and reducing the energy loss that would otherwise occur when the regulator attempts to handle large voltage differentials directly.
2Loss of energy
If capacitive voltage divider is coupled to voltage regulator, then energy efficiency improves by reducing voltage differentials, but device complexity increases due to additional components
Solution Approach 1:
The capacitive voltage divider is designed with selectable capacitor configurations that allow it to serve multiple functions: it can provide different voltage division ratios depending on which capacitors are connected, and it can adapt to different input voltage conditions. This multi-functionality reduces the need for additional dedicated components for each voltage translation scenario.
Solution Approach 2:
The capacitive voltage divider incorporates dynamically selectable capacitor connections that can be reconfigured based on operating conditions. This dynamic reconfiguration allows the system to optimize the voltage division ratio in real-time, improving energy efficiency across different operating points without requiring multiple fixed dedicated circuits.
3Adaptability or versatility
If multiple capacitors are selectably connected in the capacitive voltage divider, then adaptability to different input voltages improves, but device complexity increases
Solution Approach 1:
The system performs preliminary voltage reduction through the capacitive voltage divider before the voltage regulator operates. By pre-adjusting the voltage to a compatible range using selectable capacitor configurations, the system prepares the input for the regulator in advance, enabling the regulator to operate efficiently across a wide range of input voltages without requiring complex real-time adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves energy efficiency in low power modes by minimizing quiescent voltages and currents, achieving higher energy efficiency in voltage translation processes, and can be extended to other power management architectures beyond low power modes.
Implementation Method 1
a capacitive voltage divider (CVD) selectably coupled to either a linear voltage regulator (LVR) or a switching voltage regulator (SVR), allowing for conversion of primary supply voltages to a second supply voltage
Data Source
AI summary
A method of operating a memory sub-system includes receiving an input voltage at a power management (PM) component of a memory sub-system, where the PM component includes a capacitive voltage divider (CVD), a linear voltage regulator (LVR), and a switching voltage regulator (SVR). The method includes determining whether the input voltage corresponds to a low power mode of the memory sub-system and that the input voltage is higher than an uppermost supply voltage at which a memory component of the memory sub-system is configured to operate. The method further includes selectably coupling, responsive to a determination of the low power mode, the CVD and the LVR and sequentially reducing the input voltage by the CVD and the LVR to a supply voltage for the memory component, where the supply voltage is not higher than the uppermost supply voltage at which the memory component is configured to operate.