Capacitor Array Hard Mask Doping for Low-Leakage Trench Etching
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Solution Overview
Problem
As semiconductor devices become more highly integrated with shrinking sizes, the manufacturing process faces challenges in reducing leakage and improving yield due to close distances between components.
Innovation Solution
A method of manufacturing a capacitor array involves doping a P-type or N-type impurity in a hard mask layer before forming trenches for capacitors, which enhances etching resistance or rate, reducing source leakage and improving process yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch between semiconductor structures is shortened to increase integration, then device integration is improved, but leakage between components increases
Solution Approach 1:
The patent applies different doping concentrations to different regions of the hard mask layer. The array area receives a first doping concentration while the peripheral area receives a second doping concentration, creating local quality differences that optimize both integration and leakage prevention in respective regions
Solution Approach 2:
The patent changes the doping concentration parameter of the hard mask layer to control etching resistance. By adjusting the doping concentration, the etching rate is modified to create appropriate step differences between array and peripheral areas, thereby controlling leakage while maintaining integration
2Manufacturing precision
If the hard mask layer thickness is increased to improve etching uniformity, then manufacturing precision is improved, but high-step structures are worsened
Solution Approach 1:
The patent creates different doping concentrations in different regions of the hard mask layer, resulting in different etching rates for array and peripheral areas. This local quality difference allows the same layer thickness to produce different effective heights, reducing high-step structures while maintaining etching uniformity
Solution Approach 2:
The patent changes the doping concentration parameter to control the etching rate of the hard mask layer. By optimizing the doping concentration, the etching uniformity is improved while the resulting step structure is controlled to minimize high-step formations
3Reliability
If doping concentration in hard mask layer is increased to reduce source leakage, then reliability is improved, but etching rate is reduced
Solution Approach 1:
The patent applies different doping concentrations to different regions: a first doping concentration in the array area and a second doping concentration in the peripheral area. This allows the array area to have high etching resistance for leakage prevention while the peripheral area maintains higher etching rate for efficient processing
Solution Approach 2:
The patent applies doping selectively to only the regions where it is needed (array area for leakage prevention), rather than uniformly across the entire hard mask layer. This partial action maintains etching rate in non-critical areas while achieving leakage reduction in critical areas
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces source leakage and improves the uniformity of the hard mask layer, leading to enhanced process yield and reduced high-step structures in semiconductor devices.
Implementation Method 1
A P-type impurity is doped in the first hard mask layer exposed by the photoresist layer to form a second hard mask layer
Implementation Method 2
forming the plurality of trenches is performed by a dry etching process with halogen-based gas
Data Source
AI summary
Embodiments of this disclosure provide a method of manufacturing a capacitor array, including the following steps. A substrate including a first cap layer over the substrate, a second cap layer on the first cap layer and a first hard mask layer on the second cap layer is provided. A photoresist layer is formed on the first hard mask in the peripheral area to expose the first hard mask in the array area. An impurity is doped in the exposed first hard mask layer to form a second hard mask layer. A pattern layer is formed on the first hard mask layer and the second hard mask layer to expose exposed portions on a surface of the second hard mask layer. Trenches are formed by etching. A capacitor is formed in each of the trenches.