Capacitor Array Segmentation for IC Reliability

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Solution Overview

Problem

Semiconductor devices face challenges in achieving reliable capacitors with high capacitance stability and reduced area consumption, especially under stringent failure rate requirements due to extrinsic defect densities and increased voltage usage, which existing technologies struggle to meet.

Innovation Solution

The implementation of a capacitor array design where multiple capacitor elements are arranged in series and parallel configurations within metallization layers, with each capacitor element having a scaled capacitance to maintain overall capacitance while reducing area consumption and enhancing reliability by distributing the failure risk across multiple components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single capacitor is used to achieve high capacitance, then the capacitance value is sufficient, but the area consumption increases and reliability decreases

Engineering Contradiction:
Improvecapacitor reliabilityVSAvoidcapacitor area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The single capacitor is segmented into multiple capacitor elements (e.g., four capacitor elements) that are coupled in series and parallel configurations. Each capacitor element has a smaller area than the original single capacitor, yet the combined array maintains the required capacitance value while reducing overall area consumption and improving reliability through distributed failure risk.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The capacitor array utilizes multiple metallization layers (first metallization layer, second metallization layer, third metallization layer) to arrange capacitor elements in three-dimensional space. This vertical stacking approach allows the capacitor array to achieve high capacitance with reduced planar area by distributing capacitor elements across different layers and coupling them through vias and conductive structures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Power

If voltage usage is increased to improve performance, then the power capability increases, but the failure rate increases due to extrinsic defect densities

Engineering Contradiction:
Improvepower capabilityVSAvoidfailure rate
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The capacitor array segments the voltage stress across multiple capacitor elements coupled in series. Each capacitor element experiences a portion of the total voltage, reducing the voltage stress on individual elements and lowering the failure rate associated with high voltage usage while maintaining the overall power capability of the capacitor array.

Inventive Principle:
Principle #1Segmentation

3Reliability

If multiple capacitor elements are arranged in series and parallel, then reliability improves and area is reduced, but the device complexity increases

Engineering Contradiction:
Improvecapacitor reliabilityVSAvoidcapacitor array complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple capacitor elements are merged into a unified capacitor array structure with shared conductive structures, vias, and interconnects. The series and parallel couplings are integrated through common electrical nodes, reducing the overall complexity compared to implementing separate capacitor circuits. The merging of multiple elements into a coordinated array achieves improved reliability while managing device complexity through systematic integration.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10446534B2Capacitors in integrated circuits and methods of fabrication thereof
Publication Date: 2019.10.15 INFINEON TECHNOLOGIES AG
  • US10446534B2 patent drawing
  • US10446534B2 patent drawing
  • US10446534B2 patent drawing

AI summary

In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.