Capacitor Array Self-Calibration Using Averaged Reference Comparisons

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Solution Overview

Problem

Existing self-calibration methods for capacitors are hindered by calibration errors caused by reference voltage inaccuracies, leading to increased dynamical non-linearity errors in analog-to-digital converters (ADCs), which are costly and time-consuming to correct.

Innovation Solution

A self-calibration circuit and method that repeatedly calibrates compensation capacitors to generate an average parameter, reducing calibration errors by averaging multiple capacitance comparisons between a reference capacitor and a capacitor array, thereby adjusting the parallel connection relation between compensation capacitors and a target capacitor to approximate the capacitance of the reference capacitor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single capacitor calibration procedure is performed using a reference voltage, then the calibration process is simple and fast, but calibration errors occur due to reference voltage inaccuracies or noise

Engineering Contradiction:
Improvecalibration speedVSAvoidcalibration accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies periodic action by performing the capacitor calibration procedure multiple times in succession. Each calibration cycle uses the same reference voltage and capacitor array, but by repeating the measurement process several times and averaging the results, the system reduces the impact of random noise and transient reference voltage errors, thereby improving calibration accuracy while maintaining a relatively efficient process

Inventive Principle:
Principle #19Periodic action

2Manufacturing precision

If multiple fabrication processes or laser trimming are used to improve capacitor accuracy, then the capacitance accuracy reaches high precision, but the manufacturing cost and time increase significantly

Engineering Contradiction:
Improvecapacitor accuracyVSAvoidmanufacturing cost and time
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent implements self-service by enabling the capacitor array to calibrate itself automatically during normal operation. The system uses its own internal resources (capacitor array, reference voltage, and control logic) to perform self-diagnosis and self-correction of capacitance errors. This eliminates the need for external laser trimming equipment and multiple fabrication processes, significantly reducing manufacturing complexity and cost while achieving high precision calibration

Inventive Principle:
Principle #25Self-service

3Loss of time

If compensation capacitors are calibrated using a single comparison with reference capacitor, then the calibration process is quick, but the dynamical non-linearity error of ADC increases due to calibration errors

Engineering Contradiction:
Improvecalibration timeVSAvoidADC conversion accuracy
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent applies feedback by implementing an iterative calibration process where the results of each calibration cycle are used to adjust subsequent measurements. The system compares the capacitance values multiple times, averages the results, and uses this feedback information to determine the final compensation capacitor settings. This feedback mechanism ensures that transient errors and noise do not propagate into the final ADC conversion accuracy, thereby maintaining high reliability

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7924209B2Self-calibration circuit and method for capacitors
Publication Date: 2011.04.12 PROLIFIC TECH INC
  • US7924209B2 patent drawing
  • US7924209B2 patent drawing
  • US7924209B2 patent drawing

AI summary

A self-calibration circuit and method for capacitors are provided. A capacitor array is calibrated to approximate a reference capacitor according to an average parameter generated by calibrating the capacitor array multiple times. Since the capacitance of the compensation capacitor required to be connected to the target capacitor in parallel is determined according to the average parameter generated by performing the calibration multiple times, the error caused by a single calibration can be reduced, and meanwhile the calibration error caused by a reference voltage error or noise is reduced.