Capacitor Array Shielding Parasitic Capacitance
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Solution Overview
Problem
Existing capacitor arrays face challenges in precision due to edge definition errors, thickness gradients, and parasitic capacitance issues, which limit their adaptability for precise analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), especially in large-scaled integrated circuits.
Innovation Solution
A capacitor array design featuring a shielding structure that encloses both lower and upper electrodes, with subordinate shielding structures in multiple metal layers to reduce parasitic capacitance effects, and a matrix configuration with unit capacitors connected by upper electrode lines and arranged to minimize parasitic influences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitor area is increased to achieve required capacitance values, then capacitance is improved, but parasitic capacitance from metal lines and edge definition errors increases proportionally
Solution Approach 1:
A shielding electrode is introduced as an intermediary element between the capacitor plates and surrounding metal lines. This shielding electrode acts as a mediator that blocks parasitic capacitance coupling from adjacent conductors, allowing the capacitor to maintain its required capacitance value without being affected by parasitic effects from metal lines and interconnect structures.
Solution Approach 2:
The parasitic capacitance effect is extracted and isolated from the main capacitor structure by introducing a separate shielding electrode. The shielding electrode captures and contains the parasitic capacitance effects, separating them from the functional capacitor plates, thereby allowing the main capacitor to operate with its intended capacitance value unaffected by parasitic influences.
2Area of stationary object
If unit capacitors are made smaller to reduce area, then area is reduced, but precision is degraded due to increased relative parasitic capacitance
Solution Approach 1:
The shielding electrode serves as a protective intermediary that enables miniaturization of unit capacitors without sacrificing precision. By blocking parasitic capacitance from surrounding structures, the shielding electrode allows small capacitors to maintain accurate capacitance values, making high-precision capacitor arrays feasible in compact areas.
3Quantity of substance
If capacitors are arranged in binary-weighted ladder configuration, then capacitance ratios are achieved, but ratio errors occur due to edge definition errors and thickness gradients
Solution Approach 1:
The shielding electrode acts as a protective intermediary that isolates each capacitor in the binary-weighted ladder from parasitic effects. This shielding ensures that capacitance ratios are determined by the controlled geometry of the capacitor plates themselves, rather than being corrupted by edge definition errors or thickness gradients in the oxide layer, thereby improving ratio accuracy.
4Object-affected harmful factors
If shielding structures are added to reduce parasitic capacitance, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The shielding electrode is implemented as a thin conductive film or shell structure that can be integrated into existing capacitor fabrication processes. This thin-film approach provides effective parasitic capacitance shielding without adding significant structural complexity or occupying excessive space, maintaining manufacturing simplicity while achieving the desired parasitic reduction.
Data Source
AI summary
In a capacitor and a capacitor array configured for reducing an effect of parasitic capacitance, the capacitor array can have a matrix configuration that includes a plurality of unit capacitors. The unit capacitors include a lower electrode and an upper electrode that constitute a plate capacitor, as well as shielding structures which enclose the capacitor. The unit capacitors are connected by an upper electrode connecting line with a first direction to constitute a plurality of capacitor columns, wherein the unit capacitors are also arranged in rows, in a second direction perpendicular to the first direction, and wherein lower electrode lead lines are disposed between the capacitor columns, the lower electrode lead lines being connected to the respective lower electrodes of each of the unit capacitors.