Multilayer Capacitor Array Vertical Stacking
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Solution Overview
Problem
Conventional multilayer capacitor arrays face challenges in achieving high capacitance, preventing delamination and crosstalk between capacitor devices, and maintaining low equivalent series inductance (ESL) characteristics, especially in high-frequency circuits.
Innovation Solution
A multilayer capacitor array design featuring a capacitor body with alternating dielectric layers and internal electrodes of opposing polarities, where external electrodes are connected via leads without overlapping, forming blocks that are repeatedly deposited to ensure low ESL and prevent crosstalk, while maintaining high capacitance and preventing delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If internal electrodes are divided in the same plane to increase mounting density, then more capacitor devices can be integrated into one chip, but delamination between layers occurs and electrode area decreases causing capacitance loss
Solution Approach 1:
The patent transitions from planar division of internal electrodes to three-dimensional stacking of electrode blocks. Multiple electrode blocks are arranged vertically along the thickness direction of the capacitor body, allowing increased capacitance and mounting density without planar delamination issues. Each block maintains intact layered structure while multiple blocks provide higher overall capacitance.
Solution Approach 2:
The capacitor is divided into multiple electrode blocks, each comprising intact alternating positive and negative internal electrodes with dielectric layers. These blocks are stacked vertically rather than dividing electrodes within the same plane, maintaining structural integrity while achieving higher density through vertical segmentation.
2Productivity
If internal electrodes are divided in the same plane, then more capacitor devices can be formed, but substantial decrease of electrode area is caused generating capacitance loss
Solution Approach 1:
The patent utilizes the thickness direction (vertical dimension) to arrange multiple electrode blocks instead of dividing electrodes in the planar direction. This vertical stacking preserves the full electrode area of each block while increasing the total number of capacitor devices through additional blocks stacked along the vertical axis.
Solution Approach 2:
Multiple electrode blocks are combined vertically to form a single capacitor device with high capacitance. Each block contributes its full electrode area to the total capacitance, and the blocks work together as an integrated unit, achieving high capacitance without sacrificing individual electrode area.
3Productivity
If electrode plates are disposed in a line in the same plane, then capacitor devices can be formed, but electromagnetic interference due to stray capacitance occurs generating crosstalk
Solution Approach 1:
The patent arranges electrode blocks vertically along the thickness direction rather than disposing electrode plates in a line in the same plane. This vertical separation in the thickness direction increases physical distance between adjacent electrodes of opposite polarity from different blocks, reducing stray capacitance and preventing crosstalk while still forming functional capacitor devices.
4Area of stationary object
If conventional capacitor array structure is used, then mounting area is reduced, but ESL cannot be lowered enough for high frequency circuits
Solution Approach 1:
The patent reduces ESL by utilizing the thickness direction for vertical stacking of electrode blocks with alternating polarities. This three-dimensional arrangement shortens the current path length through the capacitor structure, thereby reducing equivalent series inductance and improving high-frequency performance while maintaining compact mounting area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively increases capacitance, reduces ESL and equivalent series resistance (ESR), and minimizes crosstalk between capacitor devices, allowing for efficient use in high-frequency circuits and compact layouts.
Implementation Method 1
a plurality of first polarity internal electrodes and second polarity internal electrodes, disposed oppositely to each other in the capacitor body, interposing the dielectric layer therebetween
Implementation Method 2
a capacitor body formed by depositing a plurality of dielectric layers
Data Source
AI summary
A multilayer capacitor array having a plurality of multilayer capacitor devices formed in a single multilayer structure, the multilayer capacitor array including: a capacitor body formed by depositing a plurality of dielectric layers and having first and second side surfaces opposite to each other; a plurality of first polarity internal electrodes and second polarity internal electrodes, disposed oppositely to each other in the capacitor body, interposing the dielectric layer there between, and formed of a single electrode plate comprising a single lead, respectively; and a plurality of first polarity external electrodes and second polarity external electrodes, formed on the first side surface and second side surface, respectively, and connected to a correspondent polarity internal electrode via the lead, the first polarity external electrode formed on the first side surface and the second polarity external electrode formed on the second side surface, wherein the numbers of the first polarity external electrodes and the second polarity external electrodes are two or more, respectively, and are identical to each other, and a total number of the multilayer capacitor devices in the multilayer capacitor array is identical to the number of the first polarity external electrodes.