Capacitor Bank Structure for Semiconductor Package Noise Reduction
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Solution Overview
Problem
Current semiconductor package structures face challenges in achieving stable voltage variation and noise reduction due to long current paths and increased solder ball size, while also dealing with high assembly costs and substrate thickness in existing capacitor configurations.
Innovation Solution
A semiconductor package structure is designed with capacitors disposed between the semiconductor device and the conductive structure, featuring double-sided decoupling capacitors, protection materials, dielectric layers, and conductive pillars to shorten the decoupling loop and increase the ball mount area, reducing manufacturing time and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If capacitors are integrated closer to the semiconductor device to shorten the decoupling loop, then noise reduction and voltage stability improve, but the substrate thickness and assembly complexity increase
Solution Approach 1:
The capacitor bank structure transitions from planar integration to three-dimensional vertical stacking, with capacitors arranged in multiple layers above the substrate. This allows the decoupling function to be achieved in the vertical dimension rather than increasing horizontal substrate area, effectively reducing the impact on substrate thickness while maintaining noise reduction performance.
Solution Approach 2:
The capacitor bank structure nests multiple capacitors within a compact vertical arrangement, where lower capacitors are positioned closer to the substrate and upper capacitors stack above them. This nested configuration maximizes the decoupling loop shortening effect while containing the overall height, effectively managing the substrate thickness constraint.
2Reliability
If more capacitors are integrated to improve voltage stability, then power supply stability improves, but device complexity and manufacturing cost increase
Solution Approach 1:
Multiple capacitors are merged into a single integrated capacitor bank structure with shared common electrodes and unified packaging. The capacitors share common first electrodes and common second electrodes, eliminating the need for separate mounting of individual capacitors and reducing overall structural complexity while maintaining the cumulative capacitance for improved voltage stability.
Solution Approach 2:
The capacitor bank structure serves multiple functions simultaneously: it provides decoupling capacitance for voltage stability, acts as a protective barrier through its encapsulation, and enables simplified manufacturing through standardized mounting procedures. The shared electrode structure also reduces the number of external connections needed.
3Ease of manufacture
If traditional capacitor mounting methods are used, then assembly process is simple, but current path is long and solder ball size increases
Solution Approach 1:
The capacitors are pre-assembled into a integrated bank structure with predetermined electrode alignments and shared connections before mounting to the substrate. This preliminary integration ensures optimal current path routing is established in advance, minimizing the decoupling loop length while maintaining a straightforward single-step mounting process.
Data Source
AI summary
A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.