Capacitive Element Bypass Circuit Using NMOS and PMOS Switches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional bypass circuitry for AC coupled inputs in high-speed applications fails to fully short out coupling capacitors, necessitating high voltage control signals and voltage translation circuitry, which is undesirable due to electrostatic discharge issues and the need for additional power supplies.
Innovation Solution
A circuit utilizing an NMOS device and two PMOS devices selectively connectable in series to bypass a capacitive element, allowing for full shunting without the need for voltage translation circuitry or high voltage power supplies, by operating in different modes based on control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high voltage NMOS switch is used to shunt the coupling capacitor, then the bypass function is achieved, but the capacitor is not fully shorted out and additional circuitry is required
Solution Approach 1:
The patent combines NMOS and PMOS switches in a complementary arrangement where both switches work together to fully shunt the coupling capacitor. The NMOS switch handles the primary bypass function while the PMOS switch compensates for the NMOS's inability to fully discharge the capacitor, achieving complete shunting without requiring additional voltage translators or high voltage supplies.
Solution Approach 2:
The patent changes the voltage parameters by using complementary devices (NMOS and PMOS) with opposite polarity characteristics. This allows the circuit to achieve full voltage range shunting capability without requiring high voltage supplies, as the complementary devices can operate with standard voltage levels while providing complete capacitor discharge.
2Reliability
If a PMOS switch is added in parallel with NMOS switch to fully shunt the capacitor, then full bypass is achieved, but high voltage control signal and voltage translator are required
Solution Approach 1:
The patent implements self-service by having the NMOS and PMOS switches control each other through their inherent complementary characteristics. The gates of the switches are connected such that when one switch turns on, it automatically enables the other switch through voltage level interaction, eliminating the need for external high voltage control signals or voltage translator circuits.
Solution Approach 2:
The patent uses asymmetric device configuration where NMOS and PMOS switches have different threshold voltages and conduction characteristics. This asymmetry is exploited to create a control mechanism where the switches naturally complement each other's operation, allowing full capacitor shunting without requiring symmetric high voltage control for both devices.
3Ease of operation
If conventional bypass circuitry is used, then bypass functionality is provided, but susceptibility to electrostatic discharge increases
Solution Approach 1:
The patent employs standard voltage level devices (NMOS and PMOS switches operating at normal voltage levels) instead of high voltage components. These standard devices have better inherent ESD protection characteristics and do not require high voltage supplies that are more susceptible to ESD events, thereby reducing overall ESD susceptibility while maintaining bypass functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively bypasses capacitive elements in both high-speed and low-speed modes without requiring voltage translation or high voltage supplies, ensuring reliable signal transmission and reducing susceptibility to electrostatic discharge.
Implementation Method 1
at least one NMOS device selectively connectable across the capacitive element to be bypassed
Implementation Method 2
at least first and second PMOS devices, the PMOS devices being selectively connectable together in series across the capacitive element to be bypassed
Data Source
AI summary
A circuit for selectively bypassing a capacitive element includes at least one NMOS device selectively connectable across the capacitive element to be bypassed, and at least first and second PMOS devices. The PMOS devices are selectively connectable together in series across the capacitive element to be bypassed. The NMOS device provides a first bypass path and the first and second PMOS devices collectively provide a second bypass path.