Capacitor Charge Sharing for Kernel Weight Normalization
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Solution Overview
Problem
Hardware acceleration of matrix operations in neural networks, such as CNNs, results in a large number of operations for processing image data, leading to impractically long processing times due to the complexity of three-dimensional matrix operations.
Innovation Solution
The implementation of a device and method using multiple cross-bar arrays with capacitive analog memory cells to perform matrix operations in parallel, where capacitor charge sharing normalizes kernel weights across multiple kernel sets, reducing error and variability, and facilitating faster processing by dividing the forward pass across multiple arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple cross-bar arrays are used to process image data in parallel, then processing speed is improved, but device complexity increases
Solution Approach 1:
The system divides the image processing task into multiple segments by using multiple cross-bar arrays, where each array processes a different kernel set simultaneously. This segmentation enables parallel processing of image patches, improving productivity while managing complexity through modular architecture
Solution Approach 2:
Multiple cross-bar arrays are merged into a unified system with shared control mechanisms and normalized kernel weights. The arrays work together as an integrated parallel processing unit, combining their computational power to achieve high-speed processing without proportionally increasing overall system complexity
2Measurement precision
If kernel weights are normalized across multiple kernel sets, then processing accuracy is improved, but additional operations are required increasing time consumption
Solution Approach 1:
Kernel weight normalization is performed in advance during the training phase, preparing normalized kernel weights before the actual image processing task. This preliminary action ensures accuracy during inference without adding time consumption during the forward pass, as the normalization is already completed
Solution Approach 2:
The system performs self-normalization of kernel weights across multiple kernel sets using a unified normalization mechanism. The normalization process is automated and integrated into the system operation, eliminating the need for manual intervention or additional external processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces processing time for matrix operations by enabling concurrent processing of image patches with multiple kernel sets, improving the speed and accuracy of operations like matrix multiplication and convolution, while maintaining consistent kernel applications.
Implementation Method 1
An analog memory cell including a capacitor stores a first kernel weight of a first kernel
Implementation Method 2
A charge connection connects the first capacitor to at least a second capacitor storing a second kernel weight such that charge is shared between the first capacitor and at least the second capacitor to normalize the first kernel weight and the second kernel weight
Data Source
AI summary
A method for multiple copies of a set of multi-kernel set operations in a hardware accelerated neural network includes a word line for receiving a pixel value of an input image. A bit line communicates a modified pixel value. An analog memory cell including a first capacitor stores a first kernel weight of a first kernel in one of a plurality of kernel sets such that the pixel value is operated on by the first kernel weight to produce the modified pixel value. A charge connection connects the first capacitor to at least a second capacitor storing a second kernel weight of a related kernel of a second one of the plurality of kernel sets such that charge is shared between the first capacitor and at least the second capacitor to normalize the first kernel weight and the second kernel weight.