Capacitor Circuit Vertical Stacking Layout Optimization
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Solution Overview
Problem
Existing capacitor circuits face challenges in achieving both a small area and high performance due to complex layout configurations and signal wiring, which complicates the realization of high-resolution or high-accuracy circuits.
Innovation Solution
The capacitor circuit design involves a capacitor array and a switch array with switch control signal lines wired between them, allowing for overlapping configurations in a plan view, which reduces circuit area and enhances performance by ensuring efficient layout wiring and uniformity of switch control signal lines and voltage supply lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all capacitors are disposed in the same island separated from surrounding regions with symmetric layout, then measurement precision is improved, but device complexity increases due to complicated layout configuration and signal wiring
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. Capacitors are disposed in multiple islands at different vertical levels (first conductive layer above substrate, second conductive layer above first conductive layer), allowing capacitors to be positioned at different heights while maintaining electrical connections through vertical conductive paths. This vertical stacking enables high-density integration without increasing planar footprint, resolving the contradiction between precision (achieved through symmetric arrangement) and complexity (reduced by eliminating extensive lateral wiring).
Solution Approach 2:
The patent implements nested positioning where the second conductive layer is disposed above the first conductive layer, and both are positioned above the substrate. This nested vertical arrangement allows multiple capacitor islands to occupy overlapping planar spaces at different vertical levels, effectively nesting functional elements within each other's projection areas. This eliminates the need for separate lateral wiring paths, significantly reducing layout complexity while maintaining the symmetric arrangement necessary for measurement precision.
2Measurement precision
If complex layout configuration and signal wiring are used to achieve high resolution, then measurement precision is improved, but area of the circuit increases
Solution Approach 1:
The patent utilizes vertical stacking to achieve high-resolution capacitance measurements without expanding circuit area. By positioning capacitor islands at different vertical levels (first and second conductive layers) with overlapping planar projections, the design achieves high integration density. The symmetric arrangement within each island maintains measurement precision, while the vertical stacking eliminates the need for extensive lateral wiring that would otherwise increase circuit area.
Solution Approach 2:
Multiple capacitor islands are nested vertically with overlapping planar projections. The second conductive layer containing capacitor islands is positioned above the first conductive layer, creating a nested configuration where functional elements occupy the same planar space at different heights. This nesting approach achieves high-resolution measurement capability through symmetric capacitor arrangements while minimizing the overall circuit footprint by eliminating separate lateral wiring regions.
3Area of stationary object
If capacitors are disposed in multiple islands at different vertical levels, then circuit area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements nested vertical stacking where the second conductive layer is positioned above the first conductive layer, with both layers containing capacitor islands that have overlapping planar projections. This nested configuration reduces circuit area by eliminating lateral wiring requirements. The design inherently addresses manufacturing precision challenges through the nested structure, where vertical alignment between layers is facilitated by the overlapping projection geometry, reducing the cumulative alignment error that would affect non-overlapping configurations.
Data Source
AI summary
A capacitor circuit includes: a capacitor array including a plurality of capacitors; a switch array including a plurality of switch circuits, the switch circuits being respectively connected to the capacitors of the capacitor array; a plurality of switch control signal lines supplied with a plurality of switch control signals; and a substrate having a major surface on which the switch circuits are formed. At least part of the capacitors of the capacitor array is formed of a first conductive layer. The switch control signal lines are formed of a second conductive layer provided between the major surface and the first conductive layer. The capacitor array and the switch array are disposed so as to overlap each other at least in part in a plan view when viewed in a normal direction of the major surface.