Capacitor Co-layout for Voltage Noise Reduction
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Solution Overview
Problem
High-speed processing units on printed circuit boards face voltage noise issues due to power supply line irregularities and thermal limitations of bypass capacitors, which are exacerbated by limited space and non-customizable component choices.
Innovation Solution
A surface mounted layout featuring a co-layout of multilayer ceramic capacitors and solid electrolytic polymer capacitors strategically positioned around the footprint of high-speed processing units to reduce voltage noise, with multilayer ceramic capacitors providing thermal stability and solid electrolytic polymer capacitors handling high switching operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If bypass capacitors are placed close to the high-speed processing unit to reduce voltage noise, then voltage noise reduction is improved, but thermal specifications are violated due to heat exposure
Solution Approach 1:
The capacitor array is segmented into multiple individual capacitor units (e.g., 4-16 capacitors) distributed across the PCB substrate. Each capacitor can be independently positioned at optimal locations relative to the heat source, allowing some capacitors to be placed closer for noise reduction while others are positioned farther away to avoid thermal damage, thus resolving the contradiction between noise reduction and thermal specification compliance
Solution Approach 2:
The solution transitions from a single-point capacitor placement to a distributed two-dimensional array of capacitors across the PCB substrate. This spatial distribution allows the system to simultaneously achieve close proximity to the heat source (for noise reduction) and adequate thermal distance (for specification compliance) by utilizing the extended PCB area as the solution space
2Object-affected harmful factors
If the PCB layout is customized for new high-speed processing units, then voltage noise reduction is improved, but device complexity and manufacturing adaptability worsen
Solution Approach 1:
The capacitor array design creates a universal PCB layout solution that can be applied across multiple high-speed processing unit models and generations. The distributed capacitor configuration provides a standardized approach that addresses voltage noise for different processors without requiring custom redesigns, thereby improving adaptability while maintaining noise reduction effectiveness
Solution Approach 2:
The patent establishes a pre-planned capacitor array footprint and placement strategy that can be applied in advance to multiple processor designs. This preliminary layout framework allows designers to quickly adapt to new high-speed processing units without extensive customization, reducing the complexity of repeated design iterations while maintaining optimal noise reduction performance
3Reliability
If more capacitors are added to handle high current draws, then voltage stability is improved, but space consumption on the PCB worsens
Solution Approach 1:
The capacitor array implements local quality by concentrating multiple small-capacitance units in specific high-noise regions near the processing unit, rather than uniformly distributing large-capacitance components. This localized approach provides targeted voltage stabilization where it is most needed while minimizing overall PCB space consumption through efficient spatial utilization
Data Source
AI summary
Disclosed are methods and systems to reduce voltage noise on a printed circuit board (PCB) through a co-layout of multilayer ceramic capacitors. In one or more embodiments, this surface mounted layout comprises a first co-layout of multilayer ceramic capacitors mounted on a first corner of a rectangular footprint of a bottom side of the PCB; a second co-layout of multilayer ceramic capacitors mounted on a second corner of the rectangular footprint diagonal to the first corner; and a first solid electrolytic polymer capacitor and a second solid electrolytic polymer capacitor mounted on the remaining corners, respectively, of the rectangular footprint. The rectangular footprint of the PCB is a footprint of a high-speed processing unit mounted on the PCB. The high-speed processing unit is mounted on a top side of the PCB opposite the bottom side comprising the first co-layout of multilayer ceramic capacitors and the second co-layout of multilayer ceramic capacitors.