Capacitor Contact Dimension Control via Damascene Process
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Solution Overview
Problem
The miniaturization of dynamic random access memory (DRAM) devices poses challenges in accurately controlling the critical dimension of capacitor contacts, affecting the reliability and performance of memory devices.
Innovation Solution
A method involving the formation of isolation structures, word line sets, bit-line structures, and dielectric layers to create capacitor contacts using a damascene process, which allows for precise control of the critical dimension and simplifies the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional contact formation methods are used, then the manufacturing process is simpler, but the critical dimension control of capacitor contacts becomes inaccurate
Solution Approach 1:
The contact formation process is segmented into multiple stages: forming first dielectric layer with first pattern, forming second dielectric layer with second pattern, and selectively removing portions. This segmentation allows independent optimization of each layer's critical dimension, achieving accurate overall contact dimension control while managing process complexity through systematic division of steps.
Solution Approach 2:
The first dielectric layer is formed with a preliminary pattern before the second dielectric layer is deposited. This preliminary structuring establishes a template that guides subsequent material deposition and removal, enabling precise control of final contact dimensions through pre-planned layer configurations rather than direct single-step formation.
2Area of moving object
If miniaturization is pursued to increase integration, then device density improves, but control of critical dimension becomes more difficult
Solution Approach 1:
The solution transitions from two-dimensional planar contact formation to three-dimensional stacked dielectric layer structures. By utilizing vertical stacking of first and second dielectric layers with different patterns, the method achieves precise lateral dimension control while accommodating miniaturized device footprints, effectively adding a vertical dimension to the fabrication approach.
Solution Approach 2:
Different regions of the dielectric structure are assigned different patterns and materials: the first dielectric layer has a first pattern in certain regions, while the second dielectric layer has a second pattern in other regions. This local differentiation allows optimized critical dimension control in specific areas, enabling accurate contact formation even as overall device dimensions are reduced for higher integration.
Data Source
AI summary
A method of manufacturing a memory device includes following steps. A first dielectric layer is formed on the substrate between bit-line structures. First trenches are formed in the first dielectric layer. A second dielectric layer is formed to fill in the first trenches. A portion of the first dielectric layer is removed, so that a top surface of the first dielectric layer is lower than a top surface of the second dielectric layer. A first mask layer is formed to cover the top surfaces of the first and second dielectric layers. A first etching process is performed to form second trenches in the first dielectric layer. A third dielectric layer is formed to fill the second trenches. The first dielectric layer is removed to form contact openings between the second and third dielectric layers. A conductive material is formed to fill in the contact openings.