Capacitor Contact Hole Profile for Void-Free Bit Line Filling
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Solution Overview
Problem
In semiconductor manufacturing, high depth-to-width ratios of capacitor contact holes lead to void formation during filling, increasing resistance values in wires, which affects conductivity.
Innovation Solution
A semiconductor structure with a substrate, bit line structures, and isolation walls, where the top width of capacitor contact holes is larger than the bottom width, and a method involving the formation of a gap in the isolation wall to reduce parasitic capacitance and prevent voids, ensuring conductive plugs with low resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the depth-to-width ratio of capacitor contact holes is increased to accommodate miniaturized dimensions, then the miniaturization of semiconductor devices is achieved, but void formation occurs during filling which increases resistance values
Solution Approach 1:
The patent applies asymmetry by designing the capacitor contact hole with different widths at the top and bottom. Specifically, the top opening width is made larger than the bottom width, creating a tapered or trapezoidal profile. This asymmetric geometry prevents void formation during the filling process while maintaining the required miniaturized dimensions, thereby resolving the contradiction between device miniaturization and filling quality.
Solution Approach 2:
The patent changes the geometric parameters of the capacitor contact hole by introducing a width variation along the depth direction. The width parameter is not kept constant but is modified to be larger at the top and smaller at the bottom. This parameter change enables proper material filling without voids while maintaining the overall miniaturized scale of the contact hole.
2Ease of manufacture
If conventional filling methods are used for high depth-to-width ratio contact holes, then the manufacturing process remains simple, but voids form in the conductive plugs increasing resistance
Solution Approach 1:
The asymmetric geometry of the capacitor contact hole (larger top opening than bottom width) enables conventional filling methods to work effectively. The tapered profile allows filling material to flow in smoothly without trapping air or forming voids, maintaining both manufacturing simplicity and filling precision simultaneously.
Solution Approach 2:
The asymmetric shape of the capacitor contact hole is prepared in advance before the filling process. This preliminary geometric configuration ensures that when conventional filling is performed, the material flows correctly without forming voids, thereby achieving high manufacturing precision without complicating the filling process.
Data Source
AI summary
A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a substrate, bit line structures and isolation walls located on side walls of the bit line structures, and capacitor contact holes. In the substrate, conductive contact regions are arranged. The conductive contact regions are exposed from the substrate. A plurality of discrete bit line structures are located on the substrate. Each of the isolation walls includes at least one isolation layer and a gap between the isolation layer and the bit line structure. Each of the capacitor contact holes is constituted by a region surrounded by the isolation walls between the adjacent bit line structures. The capacitor contact holes expose the conductive contact regions. A top width of the capacitor contact holes is larger than a bottom width thereof in a direction parallel to an arrangement direction of the bit line structures.