Capacitor Contact Ring Structure to Prevent DRAM Punch-Through
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Solution Overview
Problem
The existing DRAM devices face a punch-through problem due to the overlap between storage capacitors and bit lines, which affects the reliability and performance of the semiconductor memory cells.
Innovation Solution
A semiconductor device design that includes a conductive ring surrounding the upper portion of the capacitor contact, which prevents charge punch-through from the storage capacitor to the underlying bit line, enhancing reliability and increasing the contact margin between the storage capacitor and the capacitor contact, while eliminating the need for an additional photolithography process through self-aligning patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of stationary object
If the storage capacitors are shifted from the underlying capacitor contacts to increase capacitor area, then the capacitance of the storage capacitor is improved, but overlap between the storage capacitors and bit lines occurs causing punch through problem
Solution Approach 1:
A conductive ring is introduced as an intermediary structure between the storage capacitor and the bit line. This conductive ring surrounds the capacitor contact and is positioned between the storage capacitor and the bit line, acting as a protective barrier that prevents charge punch-through while allowing the storage capacitor to maintain its shifted position for increased area
Solution Approach 2:
The conductive ring extends in the vertical dimension (z-direction) to provide protection against punch-through, while the storage capacitor maintains its lateral shift in the horizontal plane (x-y plane) to increase area. This multi-dimensional approach allows simultaneous achievement of increased capacitance and prevented punch-through
2Volume of stationary object
If the storage capacitors are shifted from the underlying capacitor contacts to increase capacitor area, then the capacitance of the storage capacitor is improved, but overlap between the storage capacitors and bit lines occurs
Solution Approach 1:
The conductive ring serves as a spatial separator and protective intermediary that allows the storage capacitor to be positioned in the optimal location for maximum area while preventing harmful overlap with the bit line through the surrounding protective structure
3Reliability
If a conductive ring is added to surround the capacitor contact to prevent punch through, then reliability is improved, but device complexity increases
Solution Approach 1:
The conductive ring is formed by merging the same conductive material layer that forms the bit line and capacitor contact structures. This is achieved through a single continuous deposition process followed by selective patterning, combining multiple functions into a unified manufacturing flow rather than adding separate process steps
4Reliability
If a conductive ring is added to surround the capacitor contact to prevent punch through, then reliability is improved, but manufacturing process complexity increases
Solution Approach 1:
The conductive ring pattern is formed through self-aligned patterning where the ring structure automatically positions itself relative to the capacitor contact during the deposition and etching processes. The capacitor contact itself serves as the alignment reference, eliminating the need for separate photolithography alignment steps
Solution Approach 2:
The formation of the conductive ring is merged with the existing bit line and capacitor contact fabrication process. The same conductive layer is deposited continuously, and the ring pattern emerges from the same etching process that defines the other conductive structures, consolidating multiple features into a single manufacturing operation
Data Source
AI summary
A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.