Capacitor-Coupled DAC Cell Layout for Low-Noise Conversion
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Solution Overview
Problem
Existing digital-to-analog converters in delta-sigma modulators introduce noise and non-linearity due to current sources and mismatches in field effect transistors, affecting the accuracy of signal conversion.
Innovation Solution
A digital-to-analog converter design that eliminates current sources by using coupling capacitors and inverters to reduce noise, with a resonator structure to enhance signal quality, and allows for differential or single-ended outputs, minimizing thermal noise and manufacturing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If current sources are used in digital-to-analog converter cells, then the converter can provide the necessary drive current, but noise is introduced affecting conversion accuracy
Solution Approach 1:
The patent removes the current source from the converter cell architecture entirely. Instead of using a current source to provide drive current, the invention uses a capacitor connected to an inverter output, eliminating the noise source while maintaining the necessary current drive capability through the capacitor discharge mechanism.
Solution Approach 2:
The patent introduces a capacitor as an intermediary element between the digital input and the output node. This capacitor serves as a mediator that stores charge and provides current drive without requiring a noisy current source, effectively decoupling the digital control signal from the analog output while maintaining drive capability.
2Device complexity
If field effect transistors are used for signal switching, then the converter achieves compact integration, but mismatches occur affecting linearity
Solution Approach 1:
The patent removes the problematic transistor switching mechanism from the critical signal path. By using a capacitor-discharge approach controlled by simple digital inputs rather than relying on precise transistor matching, the invention eliminates linearity errors caused by manufacturing variations while maintaining compact integration.
Solution Approach 2:
The patent changes the operating principle from transistor-based current switching to capacitor-based charge discharge. This parameter change shifts the critical function from relying on transistor characteristics (which vary with manufacturing) to using capacitor properties (which are more stable and less sensitive to process variations), thereby improving linearity.
3Measurement precision
If multiple cells are used to increase resolution, then conversion accuracy improves, but noise and non-linearity accumulate
Solution Approach 1:
The patent divides the converter into multiple independent cells, each handling a portion of the conversion. By using the capacitor-discharge architecture in each cell, the segmentation allows parallel operation where noise and non-linearity do not accumulate, as each cell operates independently without the compounding effects present in traditional current-source-based multi-cell designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces noise and non-linearity, improving the accuracy of signal conversion and reducing intermodulation effects, while increasing the resolution of the converter.
Implementation Method 1
The cell has a first coupling capacitor with a second terminal connected to an output and a first inverter connected between a bias voltage and ground
Implementation Method 2
The gates of the field effect transistors forming the first inverter are connected to a data input and a first common point between the field effect transistors is connected to a first terminal of the first coupling capacitor
Data Source
AI summary
A digital-to-analog converter (10) is described which comprises at least one cell (301). The cell (301) has a first coupling capacitor (415) with a second terminal connected to an output and a first inverter (405, 410) connected between a bias voltage and ground. The gates of the field effect transistors (405, 410) forming the first inverter are connected to a data input (305) and a first common point between the field effect transistors (405, 410) is connected to a first terminal of the first coupling capacitor (415).