Capacitor-Coupled N-Type Transistor OTP Device
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Solution Overview
Problem
Existing capacitor-coupled N-type transistor-based OTP devices have limited efficiency and time window for hot carrier writing due to similar source and drain doping as ordinary NMOS transistors, requiring larger capacitor areas and additional implantations, which restricts their performance.
Innovation Solution
A capacitor-coupled N-type transistor-based OTP device with a transistor and coupling capacitor in a P-well, isolated by field oxide or STI, featuring heavily-doped N-region source and drain regions, a polysilicon top plate, and an NLDD implantation bottom plate, optimized through ion-implantation at an inclination angle for enhanced hot carrier writing efficiency, and reduced polysilicon gate width for improved capacitance coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the transistor is sized at approximately 80% of an ordinary device with the same source and drain doping, then the device can be integrated, but its efficiency and time window for hot carrier writing are limited
Solution Approach 1:
The patent changes the doping parameters of the source and drain regions by introducing NLDD (Non-Linearly Doped Drain) structures with specific doping concentrations and gradients. This modifies the electric field distribution and carrier transport characteristics, thereby improving hot carrier writing efficiency and extending the time window for programming operations.
Solution Approach 2:
The patent applies different doping qualities to different regions: the source region has one doping concentration while the drain region has a different doping concentration and gradient. This local differentiation optimizes the electric field distribution specifically in the drain region to enhance hot carrier generation and injection efficiency.
2Ease of manufacture
If the capacitor has a relatively large area due to the size of the N-well of its bottom plate, then the capacitor can be formed, but the memory cell area increases
Solution Approach 1:
The patent merges the P-well regions of the transistor and capacitor into a shared structure. The transistor and capacitor are both formed in the same P-well, eliminating the need for separate P-well formations and reducing the overall area required for the memory cell while maintaining ease of manufacturing.
Solution Approach 2:
The patent optimizes the vertical structure of the capacitor by adjusting the depth and configuration of the N-well and bottom plate in the vertical dimension, allowing for reduced lateral area while maintaining the required capacitance value through increased vertical utilization.
3Ease of manufacture
If the capacitor has a low coupling ratio and large area, then the capacitor can be formed, but the capacitance coupling efficiency decreases
Solution Approach 1:
The patent changes the geometric parameters of the capacitor, specifically optimizing the area of the bottom plate and the distance between the bottom plate and top plate. This increases the coupling ratio by enhancing the capacitive coupling between the transistor drain and the capacitor, improving programming reliability without requiring additional manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances hot carrier writing efficiency and reduces memory cell area without additional photolithography steps, optimizing capacitance coupling and utilization efficiency while maintaining performance comparable to ordinary MOS devices.
Implementation Method 1
an ion-implantation process for forming the heavily-doped N-region may comprise an implantation of N-type ions conducted at an inclination angle of 15 to 45 degrees
Implementation Method 2
the coupling capacitor having a top plate formed by a polysilicon on a substrate surface, and a bottom plate formed by an NLDD implantation region and a heavily-doped N-region
Data Source
AI summary
A capacitor-coupled N-type transistor-based one-time programmable (OTP) device is disclosed. The OTP includes a transistor and a coupling capacitor both formed in a p-well and isolated from each other by field oxide or shallow trench isolation (STI). The transistor is constructed of a gate, a source region and a drain region composed of heavily-doped N-region. The coupling capacitor has a top plat formed of polysilicon on substrate surface, and a bottom plate constructed of an NLDD region and a heavily-doped N-region in the NLDD region. In order to achieve maximum capacitance utilization, the top plate of the coupling capacitor has a width not greater than the NLDD implantation region or twice a lateral junction depth of the heavily-doped n-region. The gate of the transistor may not be wider than the top plate of the coupling capacitor such that capacitance coupling ratio of the coupling capacitor to the transistor is optimized.