Multilayer Capacitor Cover Region Segmentation for Bending Strength

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Solution Overview

Problem

Multilayer capacitors face challenges in achieving sufficient flexural strength, particularly in chip components, where high flexural strength characteristics are required for reliability and durability, especially in automotive and infotainment systems.

Innovation Solution

The design incorporates a multilayer capacitor structure with a capacitor body featuring a combination of first and second dielectric layers, internal and auxiliary electrodes, and dummy electrodes, where the thickness of the second dielectric layers in the cover regions is less than those in the active region, allowing for increased lamination of dielectric layers without expanding the chip size, thereby enhancing bending strength.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the thickness of dielectric layers in cover regions is reduced, then the number of laminated dielectric layers increases, improving bending strength, but the capacitance may be reduced

Engineering Contradiction:
Improvebending strengthVSAvoidcapacitance
Core Design Contradiction:
StrengthVSQuantity of substance

Solution Approach 1:

The capacitor is divided into an active region with first dielectric layers of greater thickness for capacitance and cover regions with second dielectric layers of lesser thickness for bending strength. This segmentation allows each region to be optimized for its specific function without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the capacitor are assigned different dielectric layer thicknesses according to their functional requirements. The active region has thicker dielectric layers to maximize capacitance, while the cover regions have thinner dielectric layers to maximize bending strength, creating a non-uniform structure optimized for local performance.

Inventive Principle:
Principle #3Local quality

2Strength

If more dielectric layers are laminated to improve bending strength, then the chip size increases, but miniaturization is compromised

Engineering Contradiction:
Improvebending strengthVSAvoidchip size
Core Design Contradiction:
StrengthVSVolume of moving object

Solution Approach 1:

The invention applies different dielectric layer thicknesses to different regions, allowing the cover regions to contribute to bending strength with thinner layers, thereby increasing the effective number of laminated layers without proportionally increasing the overall chip volume.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The solution transitions from a uniform single-dimension approach to a multi-dimensional approach by varying dielectric layer thickness across different spatial regions (active region vs. cover regions), effectively utilizing the third dimension (thickness) differently in different areas to achieve both miniaturization and strength enhancement.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Strength

If the thickness of second dielectric layers is reduced to 20%-60% of first dielectric layers, then bending strength is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvebending strengthVSAvoidthickness control precision
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The patent specifies that the second dielectric layers in cover regions have a thickness of 20%-60% of the first dielectric layers in the active region. This local quality differentiation allows optimization of bending strength in cover regions while maintaining adequate capacitance in the active region, with the ratio range providing manufacturing tolerance.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10854391B2Multilayer capacitor
Publication Date: 2020.12.01 SAMSUNG ELECTRO MECHANICS CO LTD
  • US10854391B2 patent drawing
  • US10854391B2 patent drawing
  • US10854391B2 patent drawing

AI summary

A multilayer capacitor includes a capacitor body including an active region, and upper and lower cover regions disposed on upper and lower portions of the active region, respectively. First and second external electrode are disposed on both ends of the capacitor body, respectively. The active region includes a plurality of first dielectric layers, first and second internal electrodes alternately disposed with the first dielectric layer interposed therebetween, and first and second auxiliary electrodes disposed on the first dielectric layers on which the first and second internal electrodes are disposed, respectively. The upper and lower cover regions each include a plurality of second dielectric layers having a thickness less than that of each of the first dielectric layers, and a dummy electrode disposed on the second dielectric layers.