Capacitor DAC AD Converter with Alternating Parallel Sampling
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Solution Overview
Problem
Conventional analog-to-digital (AD) converters, such as successive approximation AD converters, face inefficiencies in sampling and conversion processes due to sequential operations, which can lead to reduced speed and increased chip area requirements.
Innovation Solution
The proposed AD converter employs two capacitor DAC circuits with weighted capacitance values, operating alternately in parallel to perform sampling and conversion operations, allowing simultaneous sampling and conversion, and includes a selection circuit and control circuit to manage these operations, reducing chip area and enhancing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential sampling and conversion operations are performed in a conventional AD converter, then the conversion process is simplified, but the conversion speed is reduced and chip area increases
Solution Approach 1:
The AD converter is divided into two separate converter circuits operating in parallel. One converter performs sampling while the other performs conversion, and they alternate roles in subsequent cycles. This segmentation allows simultaneous sampling and conversion operations, doubling the effective conversion speed without requiring a single complex high-speed converter
Solution Approach 2:
The two converter circuits alternately perform sampling and conversion operations in periodic cycles. During the first cycle, converter 1 samples while converter 2 converts, then in the next cycle their roles swap. This periodic alternation enables continuous processing with both operations occurring simultaneously across different time periods, improving overall throughput
2Area of stationary object
If sequential sampling and conversion operations are performed in a conventional AD converter, then the circuit design is simpler, but the chip area required increases
Solution Approach 1:
By dividing the processing workload into two separate converter circuits that operate in parallel and alternate functions, the system achieves simultaneous sampling and conversion. This segmentation improves processing efficiency without requiring a single large high-speed converter, as each converter can be optimized for its specific function during its active phase
Solution Approach 2:
The system discards the idle state of a converter during each cycle by having one converter actively sample while the other actively converts. In the next cycle, their roles are swapped, ensuring that both converters are continuously productive. This eliminates wasted processing capacity and improves overall chip utilization efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed AD conversion by allowing simultaneous sampling and conversion operations, reducing chip area and improving processing efficiency.
Implementation Method 1
The first capacitor DAC circuit includes a plurality of first capacitors having weighted capacitance values. The second capacitor DAC circuit includes a plurality of second capacitors having weighted capacitance values.
Implementation Method 2
The connection switch is switched between on and off, connects the first node and the first input terminal when being on, and connects the second node and the second input terminal when being off.
Data Source
AI summary
In an AD converter, a first capacitor DAC circuit performs a first operation in parallel with a second operation by a second capacitor DAC circuit, and the first capacitor DAC circuit performs the second operation in parallel with the first operation by the second capacitor DAC circuit. Electric charge corresponding to an input signal is sampled in the first operation. AD conversions are sequentially performed on the basis of the electric charge sampled in each first capacitor included in a plurality of first capacitors or each second capacitor included in a plurality of second capacitors in the second operation. The first capacitor DAC circuit and the second capacitor DAC circuit alternately perform the first operation and the second operation.