Capacitor-Die Power Delivery in 3D IC Stacks for Fast Transients
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Solution Overview
Problem
Existing power delivery network (PDN) designs in IC packaging face challenges in delivering high power to IP cores with high efficiency and accommodating fast power transients while minimizing cost and maintaining performance, particularly in 3D stacked packaging architectures with limited interconnect pitch.
Innovation Solution
A microelectronic assembly with IC dies in multiple layers, utilizing interconnects with silicon-level density and capacitors, where adjacent layers are electrically coupled by interconnects with a pitch of less than 10 micrometers, and capacitor-dies provide routing and voltage regulation, enabling efficient power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional 3D stacked packaging is used, then power delivery to IP cores is achieved, but power delivery efficiency is insufficient and fast power transients cannot be accommodated
Solution Approach 1:
The patent segments the power delivery function by introducing dedicated capacitor-dies that are electrically coupled to multiple IC dies. These capacitor-dies contain decoupling capacitors that are specifically designed to handle fast power transients, separating the transient response function from the general power delivery function. This segmentation allows each component to be optimized for its specific purpose, improving overall power delivery efficiency and transient response capability.
Solution Approach 2:
The capacitor-dies serve as intermediary components between the power supply and the IP cores. They are electrically coupled to multiple IC dies through interconnects and provide localized power regulation and transient response. This intermediary structure enables efficient power delivery by placing capacitance close to the power-hungry IP cores without requiring direct connection from the main power supply, thus reducing inductance and improving transient response.
2Loss of energy
If interconnect pitch is reduced to increase density, then power delivery efficiency improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent moves the power delivery optimization from the lateral dimension (interconnect pitch on the same layer) to the vertical dimension (multiple stacked layers). By utilizing through-die vias and stacking capacitor-dies vertically, the design achieves high-density interconnectivity without requiring excessively small lateral pitch. This dimensional transition allows for efficient power delivery while maintaining manufacturable interconnect dimensions.
Solution Approach 2:
The patent implements a nested structure where capacitor-dies are stacked between and around IC dies in a multi-layer configuration. The capacitor-dies are electrically coupled to multiple IC dies through vertical interconnects, creating a nested arrangement that maximizes space utilization. This nesting approach allows for high-density power delivery networks without requiring the IC dies themselves to have reduced pitch, thereby maintaining ease of manufacture.
3Reliability
If more capacitors are added to accommodate fast power transients, then transient response improves, but device complexity and cost increase
Solution Approach 1:
The capacitor-dies are designed to perform multiple functions: they provide decoupling capacitance for fast transient response, serve as structural support between IC dies, and function as part of the power delivery network. By making the capacitor-dies multi-functional, the patent reduces the need for separate dedicated transient response components, thereby improving transient accommodation capability without proportionally increasing device complexity.
Solution Approach 2:
The patent merges the capacitor function with the structural interconnect function by integrating capacitors directly into the capacitor-dies that are stacked between IC dies. This combination eliminates the need for separate capacitor components and their associated interconnects, reducing overall device complexity while maintaining the ability to accommodate fast power transients. The capacitors are embedded within the stacked die structure, utilizing the same vertical interconnect infrastructure.
Data Source
AI summary
Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.