Capacitor Dielectric Structure to Prevent Dicing Delamination
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Solution Overview
Problem
Full-sheet doping of semiconductor wafers with phosphorus leads to delamination of dielectric structures during dicing, compromising the reliability and operation of electrical devices.
Innovation Solution
Doping the entire surface of a silicon wafer with phosphorus and selecting a dielectric structure with specific materials and thicknesses to prevent delamination, such as using thermal silicon dioxide layers of at least 20 nm thickness, and avoiding inter-metal oxide layers in saw lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If full-sheet doping with phosphorus is used to minimize manufacturing steps, then manufacturing complexity is reduced, but delamination occurs during dicing
Solution Approach 1:
The patent applies local quality by creating a phosphorus-doped region that extends to the lateral edges of the capacitor structure, specifically in the saw lanes where dicing occurs. This localized doping approach maintains the beneficial electrical properties while preventing delamination during mechanical cutting, thus resolving the contradiction between manufacturing simplicity and device reliability.
Solution Approach 2:
The patent implements preliminary action by forming the phosphorus-doped region in the substrate before depositing the dielectric structure. This pre-established doped region ensures that when dicing occurs later in the manufacturing process, the delamination-resistant structure is already in place, preventing the harmful effect before it can occur.
2Ease of manufacture
If dielectric structure is formed on phosphorus-doped substrate, then manufacturing simplicity is maintained, but adherence is reduced causing delamination
Solution Approach 1:
The patent applies local quality by creating a phosphorus-doped region with specific spatial characteristics (extending to lateral edges) that provides both electrical functionality and mechanical anchoring. This localized doped structure maintains manufacturing simplicity while enhancing adherence to prevent delamination during dicing operations.
Solution Approach 2:
The patent employs composite materials by combining the phosphorus-doped silicon substrate region with the dielectric structure in a way that creates a delamination-resistant composite. The doped silicon region acts as an intermediate layer that provides both electrical properties and mechanical bonding strength between the substrate and dielectric layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents delamination during dicing, maintaining device reliability and improving electrical properties by ensuring adherence to the substrate, while minimizing manufacturing steps.
Implementation Method 1
a dielectric layer comprising thermal silicon dioxide (SiO2) on (i.e., in contact with) the silicon substrate
Data Source
Figure 1
Figure 2A~2B
Figure 2C
AI summary
The present invention relates to an electrical device and a method for manufacturing thereof. In particular, the proposed electrical device (100) comprises a capacitor including: - a bottom electrode structure (110) comprising a silicon substrate (112), the silicon substrate (112) comprising: ∘ a region (112-D) doped with phosphorus and extending up to all lateral edges of the electrical device (100), - a dielectric structure (120) extending on the bottom electrode structure (110), the dielectric structure (120) comprising at least: ∘ a dielectric layer (121) comprising thermal silicon dioxide on the silicon substrate (112), a thickness of this layer (121) being equal to or greater than 20 nm, - a top electrode structure (130) extending on the dielectric structure (120).