DRAM Memory Cell Capacitor Dielectric Directly Against Source Drain
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Solution Overview
Problem
As integrated circuitry shrinks, the size of storage capacitors in DRAM cells decreases, leading to reduced charge retention and increased difficulty in maintaining performance, with reading operations being destructive and requiring frequent refreshes.
Innovation Solution
A memory cell design incorporating a transistor device and a capacitor with a unique configuration where one capacitor electrode is electrically coupled to the channel, allowing for non-destructive reading and reduced parasitic capacitance, enabling high read speed and extended retention time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of storage capacitor is reduced to shrink memory cell size, then the quantity of charge and retention time decreases, but smaller capacitor size is needed for denser integrated circuitry
Solution Approach 1:
The patent merges the storage capacitor function with the transistor source/drain structure by forming the capacitor dielectric directly against the source/drain region. This integration allows the capacitor to share space with the transistor structure, reducing the overall memory cell footprint while maintaining adequate charge retention capability through the direct coupling configuration.
Solution Approach 2:
The patent utilizes vertical stacking by forming the capacitor dielectric layer directly against the source/drain region in a vertical orientation. This three-dimensional arrangement allows the capacitor and transistor to occupy different spatial dimensions, enabling higher density without compromising charge retention time.
2Measurement precision
If conventional DRAM reading is performed, then the read state can be determined, but the reading act is destructive and requires immediate rewriting
Solution Approach 1:
The patent introduces a tunnel oxide layer as an intermediary between the capacitor dielectric and the source/drain region. This thin insulating barrier enables non-destructive reading by allowing charge to be sensed through the oxide without complete discharge, thereby determining the read state while preserving the stored charge and eliminating the need for immediate rewriting.
3Speed
If capacitor dielectric is formed directly against source/drain region, then parasitic capacitance is reduced and read speed increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the capacitor dielectric layer directly against the source/drain region during the transistor fabrication process itself, before subsequent processing steps. This preliminary formation ensures proper alignment and minimizes parasitic capacitance from the outset, while the dielectric material's inherent properties provide tolerance for manufacturing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables non-destructive reading, reduces refresh time, and minimizes individual memory cell size while maintaining high read speed and charge retention, even with small storage capacitance.
Implementation Method 1
a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between
Implementation Method 2
A tunnel oxide layer may be interposed between the capacitor dielectric and the source/drain regions
Implementation Method 3
the channel region between the pair of source/drain regions becomes conductive
Data Source
AI summary
A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. One of the capacitor electrodes is the channel or is electrically coupled to the channel. The other of the capacitor electrodes includes a portion of the body other than the channel. Methods are also disclosed.