High Precision Capacitor Dielectric Stack
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Solution Overview
Problem
High precision capacitors in integrated circuits face limitations due to large voltage coefficients and dielectric absorption in single-layer dielectrics, which affect the accuracy of analog-to-digital and digital-to-analog conversions.
Innovation Solution
A process involving plasma treatment of the metallic surface and deposition of composite dielectric layers, specifically silicon nitride and silicon dioxide, with pre- and post-deposition plasma treatments to reduce nonlinear behavior and improve precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single layer of dielectric material such as silicon dioxide or silicon nitride is used, then the manufacturing process is simple, but the voltage coefficient and dielectric absorption are unacceptably large
Solution Approach 1:
The patent applies composite materials by combining multiple dielectric layers (silicon nitride and silicon dioxide) with different dielectric properties to create a capacitor dielectric stack. This composite structure reduces the voltage coefficient and dielectric absorption compared to single-layer dielectrics, thereby improving capacitor precision while maintaining manufacturing feasibility through established deposition processes.
Solution Approach 2:
The patent segments the dielectric layer into multiple distinct layers (first silicon nitride layer, second silicon dioxide layer, third silicon nitride layer) with different materials and properties. This segmentation allows each layer to contribute differently to the overall dielectric performance, reducing harmful effects like voltage coefficient and dielectric absorption while maintaining制造 simplicity through modular deposition processes.
2Manufacturing precision
If composite dielectric stacks of oxide/nitride/oxide are used, then the voltage coefficient and dielectric absorption are reduced, but the process complexity increases
Solution Approach 1:
The patent applies parameter changes by systematically varying the thickness, material composition, and deposition parameters of each dielectric layer to optimize the capacitor performance. By controlling parameters such as layer thickness ratios and deposition conditions, the patent achieves low voltage coefficient and dielectric absorption while managing process complexity through parameter optimization rather than structural complexity.
Solution Approach 2:
The patent applies preliminary action by performing plasma treatments on the metallic surface before dielectric deposition and potentially between deposition steps. This preliminary surface preparation reduces dielectric absorption and improves interface quality, thereby enhancing capacitor precision without requiring complex dielectric stack structures, thus managing overall process complexity.
3Manufacturing precision
If plasma treatments are performed pre- and/or post-deposition, then the quadratic capacitance voltage coefficient is reduced and precision is improved, but the manufacturing time and process complexity increase
Solution Approach 1:
The patent applies periodic action by performing plasma treatments at specific intervals during the dielectric deposition process (pre-deposition and post-deposition). This periodic plasma treatment reduces the quadratic capacitance voltage coefficient and improves capacitor precision by modifying the dielectric layers at critical stages, while managing manufacturing time by limiting treatments to essential periodic points rather than continuous processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces the quadratic capacitance voltage coefficient, leading to improved precision and symmetry in leakage current, enhancing the performance of high precision capacitors in integrated circuits.
Implementation Method 1
performs a plasma treatment of the metallic surface
Implementation Method 2
depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate
Implementation Method 3
Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition
Data Source
AI summary
A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.