Capacitor Divider ESD Trigger Circuit With Reduced IC Area
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Solution Overview
Problem
Integrated circuit (IC) devices face increased susceptibility to electrostatic discharge (ESD) events due to advancements in process technologies that reduce transistor gate length and feature sizes, necessitating enhanced ESD protection without compromising high-speed performance or increasing power consumption.
Innovation Solution
A trigger circuit is implemented using a capacitor divider circuit with series-connected capacitors and a control device to selectively discharge a common node, decoupling control signals from voltage rail transients and turning on/off based on voltage thresholds, effectively managing ESD events by clamping or shutoff mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RC-based trigger mechanisms are used for ESD protection, then reliable ESD protection can be achieved, but the circuit occupies larger area on the IC device
Solution Approach 1:
The patent changes the fundamental parameter from resistance-based (RC circuits) to capacitance-based (series capacitors C1 and C2) triggering mechanism. This parameter change enables the same ESD protection function to be achieved with significantly reduced area occupation on the IC device, as capacitor-based triggering requires less physical space than traditional RC networks while maintaining reliable voltage threshold detection for ESD events
Solution Approach 2:
The patent extracts and removes the resistor component from the traditional RC trigger mechanism, leaving only the essential capacitive elements (C1 and C2) and control transistor T1. This extraction eliminates the need for large resistor areas while preserving the core functionality of voltage threshold detection and ESD protection triggering, thereby reducing the overall circuit footprint
2Productivity
If process technologies reduce transistor gate length and feature sizes to increase transistor density, then productivity and integration are improved, but susceptibility to ESD events increases
Solution Approach 1:
The patent implements preliminary protective action by placing the ESD protection circuit at the interface boundary before ESD events can propagate into the low-voltage core. The series capacitors C1 and C2 are pre-configured to detect voltage transients and trigger the control transistor T1 to activate protection mechanisms in advance, preventing ESD damage to sensitive high-density transistors before they occur
Solution Approach 2:
The patent introduces an intermediary ESD protection circuit positioned between the high-voltage I/O interface and the low-voltage core. This intermediary circuit, comprising capacitors C1 and C2 and control transistor T1, acts as a buffer that detects and responds to ESD events, isolating the harmful effects from the vulnerable high-density transistor regions while allowing normal operation to continue
3Reliability
If ESD protection circuits are added to protect interface circuits, then reliability against ESD events is improved, but power consumption and complexity increase
Solution Approach 1:
The patent implements periodic rather than continuous operation of the ESD protection mechanism. The control transistor T1 remains in a high-impedance state during normal operation and only activates periodically when ESD events are detected by the capacitive voltage divider (C1 and C2). This periodic triggering minimizes static power consumption while providing reliable protection when needed, avoiding the continuous power drain of always-active protection circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides reliable ESD protection across a broad range of time constants, occupying less area on the IC device compared to conventional RC-based trigger mechanisms, while maintaining trigger voltages within rated maximum voltage ranges and effectively scaling for different ESD event types.
Implementation Method 1
a first capacitor and a second capacitor connected in series at a common node... means for dividing a voltage difference between a first voltage rail and a second voltage rail
Implementation Method 2
means for selectively discharging the common node... The control device has a first terminal that is coupled to the common node and a control terminal configured to receive a control signal
Data Source
AI summary
A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.