Capacitor Electrode Coupling for Aperture Ratio
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Solution Overview
Problem
Existing electro-optical devices face challenges in increasing the electrostatic capacity of retention capacitors while maintaining a reduced surface area, due to the shared use of electrodes for both capacitors, which affects the display quality and aperture ratio.
Innovation Solution
The electro-optical device incorporates a configuration with multiple insulating layers and capacitors, where the second electrode of the first capacitor is coupled to the drain electrode via the third electrode, and the third electrode is coupled to the pixel electrode, allowing for increased electrostatic capacity and reduced surface area by optimizing the contact units and layer arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the second capacitance electrode serves as a common electrode for both the first retention capacitor and the second retention capacitor, then the device complexity is reduced, but the electrostatic capacity of the retention capacitors decreases
Solution Approach 1:
The patent divides the retention capacitor into two separate capacitors (first retention capacitor and second retention capacitor) with distinct electrode structures. Each capacitor has its own dedicated electrodes and dielectric layers, allowing independent optimization of electrostatic capacity for each capacitor while maintaining separate functional pathways.
Solution Approach 2:
The patent utilizes vertical stacking of multiple insulating layers (first insulating layer, second insulating layer, third insulating layer) to create three-dimensional capacitor structures. This layered approach increases the effective capacitance area without expanding the planar footprint, resolving the contradiction between capacity and area.
2Reliability
If a structure for coupling to the transistor and pixel electrode is disposed to the second capacitance electrode, then the electrical connectivity is improved, but the surface area of the retention capacitor increases
Solution Approach 1:
The patent embeds the coupling structures within the multi-layer insulating architecture. The second capacitance electrode is positioned between the second and third insulating layers, with coupling structures nested within this layered configuration. This nesting approach provides reliable electrical connectivity while minimizing the exposed surface area.
Solution Approach 2:
The patent introduces the third insulating layer as an intermediary between the second capacitance electrode and the pixel electrode. This intermediary layer allows for optimized coupling structures that maintain electrical connectivity while reducing the direct surface area exposure of the capacitance electrode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the electrostatic capacities of the capacitors, increases the aperture ratio, and improves the display quality by minimizing the impact of electrode coupling on capacitance, enabling more efficient light modulation and gradation display.
Implementation Method 1
a first layer having insulating properties and arranged between the base member and the pixel electrode, a second layer having insulating properties and arranged between the pixel electrode and the first layer, a third layer having insulating properties and arranged between the pixel electrode and the second layer
Implementation Method 2
a first capacitor arranged between the first layer and the second layer and including a first electrode and a second electrode arranged between the second layer and the first electrode, a second capacitor arranged between the second layer and the third layer and including a third electrode and a fourth electrode arranged between the third layer and the third electrode
Data Source
AI summary
An electro-optical device includes a base member, a pixel electrode, a first insulating layer arranged above the base member, a first capacitor arranged above the first layer and including a first electrode and a second electrode arranged above the second electrode, a second insulating layer arranged above the first capacitor, a second capacitor arranged above the second layer and including a third electrode and a fourth electrode arranged above the third electrode, a third layer insulating arranged above the second capacitor, and a transistor arranged between the base member and the first layer and including a source electrode, a drain electrode, and a gate electrode. The second electrode is coupled to the drain electrode via the third electrode, and the third electrode is coupled to the pixel electrode via the second electrode.


