Memory Capacitor Upper Electrode Stack for Reliable Contact Plugs
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Solution Overview
Problem
The miniaturization and lightweighting of electronic devices require a high degree of integration in semiconductor memory devices, making it challenging to secure the reliability of these devices due to reduced design rules.
Innovation Solution
A semiconductor memory device design that includes a substrate with a cell area and peripheral area, featuring capacitors with specific electrode structures, insulation layers, and wiring contact plugs to ensure electrical connectivity and reliability, with a stacked structure of electrode barrier, main electrode, and interface layers for improved adhesion and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If design rule for components is reduced to achieve high degree of integration, then miniaturization and lightweighting of electronic devices is achieved, but reliability of semiconductor memory device deteriorates
Solution Approach 1:
The upper electrode is divided into a stacked structure consisting of a first upper electrode layer (semiconductor material) and a second upper electrode layer (metallic material). This segmentation allows each layer to perform specific functions: the semiconductor layer provides good interface with capacitor dielectric layers, while the metallic layer ensures reliable electrical connection with wiring contact plugs, thereby maintaining reliability during miniaturization
Solution Approach 2:
The upper electrode employs composite materials by combining semiconductor material (first upper electrode layer) and metallic material (second upper electrode layer). This composite structure leverages the advantages of both materials: semiconductor material's compatibility with dielectric layers and metallic material's superior electrical conductivity and adhesion, solving the reliability issue in miniaturized devices
2Reliability
If wiring contact plugs are used to electrically connect different vertical levels, then electrical connectivity is achieved, but adhesion to insulating materials becomes challenging
Solution Approach 1:
The second upper electrode layer uses metallic material that provides excellent adhesion to the filling insulation layer and etch stop layer, ensuring strong mechanical bonding while maintaining electrical conductivity for reliable connection with wiring contact plugs
Solution Approach 2:
The upper electrode structure exhibits local quality differentiation: the first upper electrode layer (semiconductor) provides good interface quality with capacitor dielectric layers, while the second upper electrode layer (metallic) provides superior adhesion quality with insulating materials and electrical conductivity for wiring connection, allowing each region to optimize its local function
Data Source
AI summary
A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.