Capacitor Upper Electrode Design for Parasitic Capacitance Reduction
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Solution Overview
Problem
Parasitic capacitance in display devices affects the operation of transistors, leading to voltage errors in scan and light emission control signals, resulting in image quality deterioration.
Innovation Solution
The use of capacitors with upper electrodes having an area greater than the overlap area between the upper and lower electrodes, which minimizes parasitic capacitance and ensures accurate voltage levels in the driving circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional capacitor structure is used in the driving circuit, then the capacitor can store charge to maintain gate voltage, but parasitic capacitance is generated that affects the gate voltage accuracy and causes image quality deterioration
Solution Approach 1:
The patent extracts and eliminates the source of parasitic capacitance by designing the upper electrode to have an area greater than the overlap area with the lower electrode. This configuration removes the overlapping region that generates parasitic capacitance, thereby extracting the harmful element from the capacitor structure while preserving the charge storage function.
Solution Approach 2:
The patent applies asymmetry by making the upper electrode area asymmetrically larger than the lower electrode overlap area. This asymmetric design ensures that the electrodes do not fully overlap, thereby minimizing parasitic capacitance generation while maintaining sufficient capacitance for charge storage. The asymmetric configuration is key to resolving the contradiction between reliability and parasitic capacitance.
2Quantity of substance
If the capacitor electrodes have large overlap area to increase capacitance, then charge storage capacity improves, but parasitic capacitance increases causing voltage errors
Solution Approach 1:
The patent applies local quality by differentiating the functional regions of the capacitor electrodes. The upper electrode is designed with a larger area that extends beyond the overlap region, creating distinct zones: one for charge storage (overlap area) and another for minimizing parasitic effects (non-overlap area). This local differentiation allows the capacitor to maintain charge storage capacity while reducing parasitic capacitance in specific regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces parasitic capacitance, enhancing the accuracy of voltage levels and improving image quality by maintaining the intended gate-on levels for scan and light emission control signals.
Implementation Method 1
a capacitor connected between a gate and a source of the transistor
Data Source
AI summary
According to exemplary embodiments of the present disclosure, a capacitor may be connected to a gate electrode of a transistor. The capacitor includes a first gate electrode connected to the gate electrode of the transistor, a gate insulation layer formed on the first gate electrode, and an upper electrode formed on the gate insulation layer. The upper electrode is formed to cover a region where the first gate electrode and the upper electrode are overlapped. The capacitor is applicable to at least one of a light emitting driving circuit and a scan driving circuit, and at least one of the light emitting driving circuit and the scan driving circuit may be included in a display device.