Capacitor Electrode Dimension Control via Passivation Hard Mask
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Solution Overview
Problem
The existing methods for fabricating semiconductor devices with integrated capacitor devices face challenges in achieving uniformity and controlled capacitance due to non-uniform wet etching processes, leading to inconsistent specifications and center frequency variations in miniaturized electronic products.
Innovation Solution
The method involves forming a semiconductor device by providing a substrate, depositing conductive and insulating layers, and patterning a thin second conductive layer after the first passivation layer is formed, using the passivation layer as a hard mask to control the electrode dimension and reduce over-etching, thereby eliminating the need for lithography and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wet etching process is used for patterning the second conductive layer, then the patterning can be performed, but the etching is non-uniform causing critical dimension control issues and over/under etching
Solution Approach 1:
The passivation layer is deposited and patterned before the second conductive layer is formed. This preliminary patterning creates a hard mask that defines the exact dimensions of the capacitor electrode, eliminating the need for subsequent etching of the conductive layer and ensuring precise critical dimension control.
Solution Approach 2:
The passivation layer serves as an intermediary hard mask between the patterning process and the second conductive layer. This intermediary layer allows for precise pattern transfer without directly etching the conductive material, thereby achieving uniform dimensions and preventing over- or under-etching.
2Productivity
If the second conductive layer is patterned before passivation layer deposition, then the capacitor electrode can be formed, but over-etching occurs affecting capacitance characteristics and uniformity
Solution Approach 1:
The passivation layer is deposited and patterned in advance before the second conductive layer is formed. This preliminary action establishes precise dimensional boundaries that prevent over-etching, ensuring uniform capacitance characteristics across all devices.
Solution Approach 2:
The conventional sequence is inverted: instead of patterning the conductive layer first and then depositing passivation, the passivation layer is patterned first to create a hard mask, followed by deposition of the second conductive layer. This inversion eliminates etching variability and ensures reliable capacitance uniformity.
3Manufacturing precision
If additional process steps are added to improve capacitance control, then manufacturing precision improves, but cycle time and cost increase
Solution Approach 1:
The passivation layer serves dual functions: as a protective passivation layer and as a hard mask for patterning the capacitor electrode. By combining these two functions into a single layer and process step, the method achieves precise capacitance control without adding extra process steps, thereby maintaining short cycle times and low costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved uniformity and repeatability of capacitance, reduced process steps, shorter cycle times, and lower costs, while maintaining the quality of semiconductor devices by preventing over-etching and enhancing the integration of passive components like capacitors and inductors.
Implementation Method 1
patterning a thin second conductive layer after the first passivation layer is formed, using the passivation layer as a hard mask to control the electrode dimension and reduce over-etching
Implementation Method 2
depositing conductive and insulating layers
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.